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[PowerPC] Fix vector extend result types in BUILD_VECTOR lowering #159398

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Merged
merged 1 commit into from
Sep 19, 2025
Merged

[PowerPC] Fix vector extend result types in BUILD_VECTOR lowering #159398

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6 changes: 5 additions & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9904,20 +9904,24 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SmallVector<SDValue, 16> Ops(16, C);
SDValue BV = DAG.getBuildVector(MVT::v16i8, dl, Ops);
unsigned IID;
EVT VT;
switch (SplatSize) {
default:
llvm_unreachable("Unexpected type for vector constant.");
case 2:
IID = Intrinsic::ppc_altivec_vupklsb;
VT = MVT::v8i16;
break;
case 4:
IID = Intrinsic::ppc_altivec_vextsb2w;
VT = MVT::v4i32;
break;
case 8:
IID = Intrinsic::ppc_altivec_vextsb2d;
VT = MVT::v2i64;
break;
}
SDValue Extend = BuildIntrinsicOp(IID, BV, DAG, dl);
SDValue Extend = BuildIntrinsicOp(IID, BV, DAG, dl, VT);
return DAG.getBitcast(Op->getValueType(0), Extend);
}
assert(!IsSplat64 && "Unhandled 64-bit splat pattern");
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/PowerPC/splat-extend.ll
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Expand Up @@ -48,3 +48,21 @@ define dso_local noundef <2 x i64> @v11l() local_unnamed_addr {
entry:
ret <2 x i64> splat (i64 -11)
}

declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>)

define i32 @crash(ptr %p) {
; CHECK-LABEL: crash:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltib v2, 127
; CHECK-NEXT: vextsb2w v2, v2
; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: stxv v2, 0(0)
; CHECK-NEXT: blr
entry:
store <4 x i32> <i32 127, i32 127, i32 127, i32 127>, ptr %p, align 16
%0 = call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>)
store <4 x i32> %0, ptr null, align 16
ret i32 0
}