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[AMDGPU] Update documentation about DWARF registers mapping. NFC #159447

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Sep 17, 2025
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[AMDGPU] Update documentation about DWARF registers mapping. NFC #159447

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8 changes: 4 additions & 4 deletions llvm/docs/AMDGPUUsage.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -2964,12 +2964,9 @@ mapping.
1088-1129 SGPR64-SGPR105 32 Scalar General Purpose Registers.
1130-1535 *Reserved* *Reserved for future Scalar
General Purpose Registers.*
1536-1791 VGPR0-VGPR255 32*32 Vector General Purpose Registers
1536-2047 VGPR0-VGPR511 32*32 Vector General Purpose Registers
when executing in wavefront 32
mode.
1792-2047 *Reserved* *Reserved for future Vector
General Purpose Registers when
executing in wavefront 32 mode.*
2048-2303 AGPR0-AGPR255 32*32 Vector Accumulation Registers
when executing in wavefront 32
mode.
Expand All @@ -2988,6 +2985,9 @@ mapping.
3328-3583 *Reserved* *Reserved for future Vector
Accumulation Registers when
executing in wavefront 64 mode.*
3584-4095 VGPR512-VGPR1023 32*32 Second Block of Vector General
Purpose Registers When executing
in wavefront 32 mode
============== ================= ======== ==================================

The vector registers are represented as the full size for the wavefront. They
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