[RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550.

[topperc]

cat /proc/cpuinfo from HiFive Premier board

processor : 0
hart : 0
isa : rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf
mmu : sv48
mvendorid : 0x489
marchid : 0x8000000000000008
mimpid : 0x6220425

[llvmbot]

@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

cat /proc/cpuinfo from HiFive Premier board

processor : 0
hart : 0
isa : rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf
mmu : sv48
mvendorid : 0x489
marchid : 0x8000000000000008
mimpid : 0x6220425

---

Full diff: https://github.com/llvm/llvm-project/pull/159465.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+5-1)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 57b415dc713ac..f5f307fd214d7 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -387,7 +387,11 @@ def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,
                                        FeatureStdExtC,
                                        FeatureStdExtZba,
                                        FeatureStdExtZbb],
-                                      SiFiveP500TuneFeatures>;
+                                      SiFiveP500TuneFeatures> {
+  let MVendorID = 0x489;
+  let MArchID = 0x8000000000000008;
+  let MImpID = 0x6220425;
+}
 
 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                       !listconcat(RVA22U64Features,

[wangpc-pp]

Please add a test in clang/test/CodeGen/RISCV/builtin-cpu-is.c.

[wangpc-pp]

LGTM.