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[RISCV] Update the vector integer division cycle in SiFive7 scheduling model #159468

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Sep 18, 2025
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[RISCV] Update the vector integer division cycle in SiFive7 scheduling model #159468

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7 changes: 5 additions & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Original file line number Diff line number Diff line change
Expand Up @@ -694,8 +694,11 @@ multiclass SiFive7WriteResBase<int VLEN,

foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c, 4));
// One bit at a time, but up to four elements can be processed at a time.
// Add 3 to number of elements to ensure the group formed by remainder
// elements are accounted for.
defvar Cycles =
!mul(sew, !div(!add(3, SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c), 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULSEWWriteResMXSEW<"WriteVIDivV", [VCQ, VA1], mx, sew, IsWorstCase>;
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 359
# CHECK-NEXT: Total Cycles: 261
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 356.0
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 258.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -29,9 +29,9 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -45,14 +45,14 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 356.00 2.00 - -
# CHECK-NEXT: - - 2.00 - 258.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@ vdiv.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 91
# CHECK-NEXT: Total Cycles: 85
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.04
# CHECK-NEXT: IPC: 0.04
# CHECK-NEXT: Block RThroughput: 88.0
# CHECK-NEXT: uOps Per Cycle: 0.05
# CHECK-NEXT: IPC: 0.05
# CHECK-NEXT: Block RThroughput: 82.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -29,9 +29,9 @@ vdiv.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 64 64.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 16 16.00 vdiv.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -45,11 +45,11 @@ vdiv.vv v12, v12, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 88.00 2.00 - -
# CHECK-NEXT: - - 2.00 - 82.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: - - - - 57.00 1.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - - - 65.00 1.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: - - - - 31.00 1.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vdiv.vv v12, v12, v12
26 changes: 13 additions & 13 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
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Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,13 @@ vdivu.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 574
# CHECK-NEXT: Total Cycles: 648
# CHECK-NEXT: Total uOps: 8

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 571.0
# CHECK-NEXT: Block RThroughput: 645.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -34,13 +34,13 @@ vdivu.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -54,18 +54,18 @@ vdivu.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 571.00 5.00 - -
# CHECK-NEXT: - - 3.00 - 645.00 5.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: - - - - 113.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 113.00 1.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
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Expand Up @@ -10,13 +10,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 485
# CHECK-NEXT: Total Cycles: 261
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 482.0
# CHECK-NEXT: Block RThroughput: 258.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -28,8 +28,8 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -43,13 +43,13 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 482.00 2.00 - -
# CHECK-NEXT: - - 1.00 - 258.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s
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Expand Up @@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 244
# CHECK-NEXT: Total Cycles: 132
# CHECK-NEXT: Total uOps: 2

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 241.0
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 129.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,7 +26,7 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -40,12 +40,12 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 241.00 1.00 - -
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s
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Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 2834
# CHECK-NEXT: Total Cycles: 2050
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 2834.0
# CHECK-NEXT: Block RThroughput: 2050.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -30,9 +30,9 @@ vdiv.vv v8, v8, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1920 1920.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 912 912.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -46,13 +46,13 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2834.00 2.00 - -
# CHECK-NEXT: - - 1.00 - 2050.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 1921.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 913.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s
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Expand Up @@ -12,13 +12,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 118
# CHECK-NEXT: Total Cycles: 132
# CHECK-NEXT: Total uOps: 2

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 115.0
# CHECK-NEXT: Block RThroughput: 129.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -30,7 +30,7 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -44,12 +44,12 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s
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Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 118
# CHECK-NEXT: Total Cycles: 132
# CHECK-NEXT: Total uOps: 2

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 115.0
# CHECK-NEXT: Block RThroughput: 129.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -31,7 +31,7 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
Expand All @@ -45,12 +45,12 @@ vdiv.vv v8, v8, v12

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
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