[Hexagon] Added lowering for sint_to_fp from v32i1 to v32f32

[pkarveti]

The transformation pattern is identical to the uint_to_fp
conversion from v32i1 to v32f32.

[llvmbot]

@llvm/pr-subscribers-backend-hexagon

Author: None (pkarveti)

Changes

The transformation pattern is identical to the
uint_to_fp conversion from v32i1 to v32f32.

---

Full diff: https://github.com/llvm/llvm-project/pull/159507.diff

2 Files Affected:

• (modified) llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (+3-2)
• (renamed) llvm/test/CodeGen/Hexagon/isel-inttofp-v32i1tov32f32.ll (+7)

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index d0dfa47468705..004050407e556 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -449,6 +449,7 @@ HexagonTargetLowering::initializeHVXLowering() {
   // Include cases which are not hander earlier
   setOperationAction(ISD::UINT_TO_FP, MVT::v32i1, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::v64i1, Custom);
+  setOperationAction(ISD::SINT_TO_FP, MVT::v32i1, Custom);
 
   setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT});
 }
@@ -2337,7 +2338,7 @@ HexagonTargetLowering::LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const {
   return ExpandHvxFpToInt(Op, DAG);
 }
 
-// For vector type v32i1 uint_to_fp to v32f32:
+// For vector type v32i1 uint_to_fp/sint_to_fp to v32f32:
 // R1 = #1, R2 holds the v32i1 param
 // V1 = vsplat(R1)
 // V2 = vsplat(R2)
@@ -2464,7 +2465,7 @@ HexagonTargetLowering::LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const {
   MVT IntTy = ty(Op.getOperand(0)).getVectorElementType();
   MVT FpTy = ResTy.getVectorElementType();
 
-  if (Op.getOpcode() == ISD::UINT_TO_FP) {
+  if (Op.getOpcode() == ISD::UINT_TO_FP || Op.getOpcode() == ISD::SINT_TO_FP) {
     if (ResTy == MVT::v32f32 && ty(Op.getOperand(0)) == MVT::v32i1)
       return LowerHvxPred32ToFp(Op, DAG);
     if (ResTy == MVT::v64f16 && ty(Op.getOperand(0)) == MVT::v64i1)
diff --git a/llvm/test/CodeGen/Hexagon/isel-uinttofp-v32i1tov32f32.ll b/llvm/test/CodeGen/Hexagon/isel-inttofp-v32i1tov32f32.ll
similarity index 83%
rename from llvm/test/CodeGen/Hexagon/isel-uinttofp-v32i1tov32f32.ll
rename to llvm/test/CodeGen/Hexagon/isel-inttofp-v32i1tov32f32.ll
index dfb2bc83537dc..f5bf8e79b14db 100644
--- a/llvm/test/CodeGen/Hexagon/isel-uinttofp-v32i1tov32f32.ll
+++ b/llvm/test/CodeGen/Hexagon/isel-inttofp-v32i1tov32f32.ll
@@ -22,4 +22,11 @@ define <32 x float> @uitofp_i1(<32 x i16> %in0, <32 x i16> %in1) #0
    ret <32 x float> %out
 }
 
+define <32 x float> @sitofp_i1(<32 x i16> %in0, <32 x i16> %in1) #0
+{
+   %q1 = icmp eq <32 x i16> %in0, %in1
+   %fp0 = sitofp <32 x i1> %q1 to <32 x float>
+   %out = fadd <32 x float> %fp0, %fp0
+   ret <32 x float> %out
+}
 attributes #0 = { nounwind readnone "target-cpu"="hexagonv79" "target-features"="+hvxv79,+hvx-length128b" }