[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips2 #159538
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@llvm/pr-subscribers-backend-mips Author: None (yingopq) ChangesFix #145411. Full diff: https://github.com/llvm/llvm-project/pull/159538.diff 2 Files Affected:
diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index 199474fbd82d7..c8868157811d2 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -747,20 +747,41 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
llvm_unreachable("Unknown pseudo atomic!");
}
+ bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
const BasicBlock *LLVM_BB = BB.getBasicBlock();
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *loop1MBB;
+ MachineBasicBlock *loop2MBB;
+ if (NoMovnInstr) {
+ loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
+ loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
+ }
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MachineFunction::iterator It = ++BB.getIterator();
MF->insert(It, loopMBB);
+ if (NoMovnInstr) {
+ MF->insert(It, loop1MBB);
+ MF->insert(It, loop2MBB);
+ }
MF->insert(It, exitMBB);
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
BB.addSuccessor(loopMBB, BranchProbability::getOne());
- loopMBB->addSuccessor(exitMBB);
- loopMBB->addSuccessor(loopMBB);
+ if (NoMovnInstr) {
+ loopMBB->addSuccessor(loop1MBB);
+ loopMBB->addSuccessor(loop2MBB);
+ } else {
+ loopMBB->addSuccessor(exitMBB);
+ loopMBB->addSuccessor(loopMBB);
+ }
loopMBB->normalizeSuccProbs();
+ if (NoMovnInstr) {
+ loop1MBB->addSuccessor(loop2MBB);
+ loop2MBB->addSuccessor(loopMBB);
+ loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
+ }
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
@@ -803,7 +824,7 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
BuildMI(loopMBB, DL, TII->get(OR), Scratch)
.addReg(Scratch)
.addReg(Scratch2);
- } else {
+ } else if (STI->hasMips4() || STI->hasMips32()) {
// max: move Scratch, OldVal
// movn Scratch, Incr, Scratch2, Scratch
// min: move Scratch, OldVal
@@ -815,6 +836,38 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
.addReg(Incr)
.addReg(Scratch2)
.addReg(Scratch);
+ } else {
+ // if min:
+ // loopMBB: move Scratch, OldVal
+ // beq Scratch2_32, 0, loop1MBB
+ // j loop2MBB
+ // loop1MBB: move Scratch, Incr
+ // loop2MBB: sc $2, 0($4)
+ // beqz $2, $BB0_1
+ // nop
+ //
+ // if max:
+ // loopMBB: move Scratch, Incr
+ // beq Scratch2_32, 0, loop1MBB
+ // j loop2MBB
+ // loop1MBB: move Scratch, OldVal
+ // loop2MBB: sc $2, 0($4)
+ // beqz $2, $BB0_1
+ // nop
+ if (IsMin) {
+ BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(OldVal).addReg(ZERO);
+ BuildMI(loop1MBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
+ } else {
+ BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
+ BuildMI(loop1MBB, DL, TII->get(OR), Scratch)
+ .addReg(OldVal)
+ .addReg(ZERO);
+ }
+ BuildMI(loopMBB, DL, TII->get(BEQ))
+ .addReg(Scratch2_32)
+ .addReg(ZERO)
+ .addMBB(loop1MBB);
+ BuildMI(loopMBB, DL, TII->get(Mips::B)).addMBB(loop2MBB);
}
} else if (Opcode) {
@@ -830,20 +883,35 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
}
- BuildMI(loopMBB, DL, TII->get(SC), Scratch)
- .addReg(Scratch)
- .addReg(Ptr)
- .addImm(0);
- BuildMI(loopMBB, DL, TII->get(BEQ))
- .addReg(Scratch)
- .addReg(ZERO)
- .addMBB(loopMBB);
+ if (NoMovnInstr) {
+ BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
+ .addReg(Scratch)
+ .addReg(Ptr)
+ .addImm(0);
+ BuildMI(loop2MBB, DL, TII->get(BEQ))
+ .addReg(Scratch)
+ .addReg(ZERO)
+ .addMBB(loopMBB);
+ } else {
+ BuildMI(loopMBB, DL, TII->get(SC), Scratch)
+ .addReg(Scratch)
+ .addReg(Ptr)
+ .addImm(0);
+ BuildMI(loopMBB, DL, TII->get(BEQ))
+ .addReg(Scratch)
+ .addReg(ZERO)
+ .addMBB(loopMBB);
+ }
NMBBI = BB.end();
I->eraseFromParent();
LivePhysRegs LiveRegs;
computeAndAddLiveIns(LiveRegs, *loopMBB);
+ if (!STI->hasMips4() && !STI->hasMips32()) {
+ computeAndAddLiveIns(LiveRegs, *loop1MBB);
+ computeAndAddLiveIns(LiveRegs, *loop2MBB);
+ }
computeAndAddLiveIns(LiveRegs, *exitMBB);
return true;
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index 85bf6d02c7d8f..5d44686ece4ec 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -12,6 +12,12 @@
; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6
; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL
; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6
+;
+; // mips2 does not test i16 and i8.
+; RUN: if grep -q "skip-test" %s; then \
+; RUN: sed -e '/define.*@\(test_max_16\|test_umax_16\|test_min_16\|test_umin_16\)/,/^}$/d' \
+; RUN: -e '/define.*@\(test_max_8\|test_umax_8\|test_min_8\|test_umin_8\)/,/^}$/d' %s > %t.filtered.ll; \
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips2 -verify-machineinstrs %t.filtered.ll -o - | FileCheck %s --check-prefix=MIPS2; fi
define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-LABEL: test_max_32:
@@ -31,6 +37,33 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-NEXT: jr $ra
; MIPS-NEXT: nop
;
+; MIPS2-LABEL: test_max_32:
+; MIPS2: # %bb.0: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: $BB0_1: # %entry
+; MIPS2-NEXT: # =>This Inner Loop Header: Depth=1
+; MIPS2-NEXT: ll $2, 0($4)
+; MIPS2-NEXT: slt $3, $2, $5
+; MIPS2-NEXT: move $1, $5
+; MIPS2-NEXT: beqz $3, $BB0_3
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.2: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB0_1 Depth=1
+; MIPS2-NEXT: b $BB0_4
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: $BB0_3: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB0_1 Depth=1
+; MIPS2-NEXT: move $1, $2
+; MIPS2-NEXT: $BB0_4: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB0_1 Depth=1
+; MIPS2-NEXT: sc $1, 0($4)
+; MIPS2-NEXT: beqz $1, $BB0_1
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.5: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: jr $ra
+; MIPS2-NEXT: nop
+;
; MIPSR6-LABEL: test_max_32:
; MIPSR6: # %bb.0: # %entry
; MIPSR6-NEXT: sync
@@ -251,6 +284,33 @@ define i32 @test_min_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-NEXT: jr $ra
; MIPS-NEXT: nop
;
+; MIPS2-LABEL: test_min_32:
+; MIPS2: # %bb.0: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: $BB1_1: # %entry
+; MIPS2-NEXT: # =>This Inner Loop Header: Depth=1
+; MIPS2-NEXT: ll $2, 0($4)
+; MIPS2-NEXT: slt $3, $2, $5
+; MIPS2-NEXT: move $1, $2
+; MIPS2-NEXT: beqz $3, $BB1_3
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.2: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB1_1 Depth=1
+; MIPS2-NEXT: b $BB1_4
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: $BB1_3: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB1_1 Depth=1
+; MIPS2-NEXT: move $1, $5
+; MIPS2-NEXT: $BB1_4: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB1_1 Depth=1
+; MIPS2-NEXT: sc $1, 0($4)
+; MIPS2-NEXT: beqz $1, $BB1_1
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.5: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: jr $ra
+; MIPS2-NEXT: nop
+;
; MIPSR6-LABEL: test_min_32:
; MIPSR6: # %bb.0: # %entry
; MIPSR6-NEXT: sync
@@ -471,6 +531,33 @@ define i32 @test_umax_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-NEXT: jr $ra
; MIPS-NEXT: nop
;
+; MIPS2-LABEL: test_umax_32:
+; MIPS2: # %bb.0: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: $BB2_1: # %entry
+; MIPS2-NEXT: # =>This Inner Loop Header: Depth=1
+; MIPS2-NEXT: ll $2, 0($4)
+; MIPS2-NEXT: sltu $3, $2, $5
+; MIPS2-NEXT: move $1, $5
+; MIPS2-NEXT: beqz $3, $BB2_3
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.2: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB2_1 Depth=1
+; MIPS2-NEXT: b $BB2_4
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: $BB2_3: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB2_1 Depth=1
+; MIPS2-NEXT: move $1, $2
+; MIPS2-NEXT: $BB2_4: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB2_1 Depth=1
+; MIPS2-NEXT: sc $1, 0($4)
+; MIPS2-NEXT: beqz $1, $BB2_1
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.5: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: jr $ra
+; MIPS2-NEXT: nop
+;
; MIPSR6-LABEL: test_umax_32:
; MIPSR6: # %bb.0: # %entry
; MIPSR6-NEXT: sync
@@ -691,6 +778,33 @@ define i32 @test_umin_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-NEXT: jr $ra
; MIPS-NEXT: nop
;
+; MIPS2-LABEL: test_umin_32:
+; MIPS2: # %bb.0: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: $BB3_1: # %entry
+; MIPS2-NEXT: # =>This Inner Loop Header: Depth=1
+; MIPS2-NEXT: ll $2, 0($4)
+; MIPS2-NEXT: sltu $3, $2, $5
+; MIPS2-NEXT: move $1, $2
+; MIPS2-NEXT: beqz $3, $BB3_3
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.2: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB3_1 Depth=1
+; MIPS2-NEXT: b $BB3_4
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: $BB3_3: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB3_1 Depth=1
+; MIPS2-NEXT: move $1, $5
+; MIPS2-NEXT: $BB3_4: # %entry
+; MIPS2-NEXT: # in Loop: Header=BB3_1 Depth=1
+; MIPS2-NEXT: sc $1, 0($4)
+; MIPS2-NEXT: beqz $1, $BB3_1
+; MIPS2-NEXT: nop
+; MIPS2-NEXT: # %bb.5: # %entry
+; MIPS2-NEXT: sync
+; MIPS2-NEXT: jr $ra
+; MIPS2-NEXT: nop
+;
; MIPSR6-LABEL: test_umin_32:
; MIPSR6: # %bb.0: # %entry
; MIPSR6-NEXT: sync
@@ -893,7 +1007,7 @@ entry:
ret i32 %0
}
-define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) {
+define i16 @test_max_16(ptr nocapture %ptr, i16 signext %val) #0 {
; MIPS-LABEL: test_max_16:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -1433,7 +1547,7 @@ entry:
ret i16 %0
}
-define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) {
+define i16 @test_min_16(ptr nocapture %ptr, i16 signext %val) #0 {
; MIPS-LABEL: test_min_16:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -1972,7 +2086,7 @@ entry:
ret i16 %0
}
-define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) {
+define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) #0 {
; MIPS-LABEL: test_umax_16:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -2510,7 +2624,7 @@ entry:
ret i16 %0
}
-define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) {
+define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) #0 {
; MIPS-LABEL: test_umin_16:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -3049,7 +3163,7 @@ entry:
}
-define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) {
+define i8 @test_max_8(ptr nocapture %ptr, i8 signext %val) #0 {
; MIPS-LABEL: test_max_8:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -3588,7 +3702,7 @@ entry:
ret i8 %0
}
-define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) {
+define i8 @test_min_8(ptr nocapture %ptr, i8 signext %val) #0 {
; MIPS-LABEL: test_min_8:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -4127,7 +4241,7 @@ entry:
ret i8 %0
}
-define i8 @test_umax_8(ptr nocapture %ptr, i8 signext %val) {
+define i8 @test_umax_8(ptr nocapture %ptr, i8 signext %val) #0 {
; MIPS-LABEL: test_umax_8:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -4665,7 +4779,7 @@ entry:
ret i8 %0
}
-define i8 @test_umin_8(ptr nocapture %ptr, i8 signext %val) {
+define i8 @test_umin_8(ptr nocapture %ptr, i8 signext %val) #0 {
; MIPS-LABEL: test_umin_8:
; MIPS: # %bb.0: # %entry
; MIPS-NEXT: addiu $sp, $sp, -8
@@ -5202,3 +5316,5 @@ entry:
%0 = atomicrmw umin ptr %ptr, i8 %val seq_cst
ret i8 %0
}
+
+attributes #0 = { "skip-test" }
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Fix #145411.