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[RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced #159715

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[RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced #159715

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42 changes: 39 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17489,9 +17489,18 @@ struct CombineResult {
Passthru = DAG.getUNDEF(Root->getValueType(0));
break;
}
return DAG.getNode(TargetOpcode, SDLoc(Root), Root->getValueType(0),
LHS.getOrCreateExtendedOp(Root, DAG, Subtarget, LHSExt),
RHS.getOrCreateExtendedOp(Root, DAG, Subtarget, RHSExt),
SDValue L = LHS.getOrCreateExtendedOp(Root, DAG, Subtarget, LHSExt);
SDValue R = RHS.getOrCreateExtendedOp(Root, DAG, Subtarget, RHSExt);
// Return SDValue() if the instructions are not reduced.
if (L->getOpcode() == Root->getOperand(0).getOpcode() &&
(R->getOpcode() == RISCVISD::VZEXT_VL ||
R->getOpcode() == RISCVISD::VSEXT_VL) &&
(R->getOperand(0).getOpcode() != ISD::SPLAT_VECTOR &&
R->getOperand(0).getOpcode() != RISCVISD::VMV_V_X_VL &&
R->getOperand(0).getOpcode() != ISD::INSERT_SUBVECTOR))
return SDValue();

return DAG.getNode(TargetOpcode, SDLoc(Root), Root->getValueType(0), L, R,
Passthru, Mask, VL);
}
};
Expand Down Expand Up @@ -17740,6 +17749,30 @@ static SDValue combineOp_VLToVWOp_VL(SDNode *N,
if (!NodeExtensionHelper::isSupportedRoot(N, Subtarget))
return SDValue();

SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
unsigned Opc0 = Op0.getOpcode();
unsigned Opc1 = Op1.getOpcode();
// Do not combine to the 'vw' instructions if the number of extended
// instructions cannot be reduced.
// vx and vi, if v is ext_mf4/ext_mf8
// vv, if op0 is ext_mf4/ext_mf8 and op1 is ext_mf8(except: imm and scalar)
if ((Opc0 == RISCVISD::VZEXT_VL || Opc0 == RISCVISD::VSEXT_VL ||
Opc0 == ISD::ZERO_EXTEND || Opc0 == ISD::SIGN_EXTEND) &&
(N->getValueType(0).getScalarSizeInBits() >
Op0.getOperand(0)->getValueType(0).getScalarSizeInBits() * 2) &&
(Opc1 == ISD::SPLAT_VECTOR || Opc1 == RISCVISD::VMV_V_X_VL ||
Opc1 == ISD::INSERT_SUBVECTOR ||
((Opc1 == RISCVISD::VZEXT_VL || Opc1 == RISCVISD::VSEXT_VL ||
Opc1 == ISD::ZERO_EXTEND || Opc1 == ISD::SIGN_EXTEND) &&
Op1.getOperand(0).getOpcode() != ISD::SPLAT_VECTOR &&
Op1.getOperand(0).getOpcode() != RISCVISD::VMV_V_X_VL &&
Op1.getOperand(0).getOpcode() != ISD::INSERT_SUBVECTOR &&
Op1->getValueType(0).getScalarSizeInBits() >
Op1.getOperand(0)->getValueType(0).getScalarSizeInBits() * 4))) {
return SDValue();
}

SmallVector<SDNode *> Worklist;
SmallPtrSet<SDNode *, 8> Inserted;
Worklist.push_back(N);
Expand Down Expand Up @@ -17817,6 +17850,9 @@ static SDValue combineOp_VLToVWOp_VL(SDNode *N,
ValuesToReplace.reserve(CombinesToApply.size());
for (CombineResult Res : CombinesToApply) {
SDValue NewValue = Res.materialize(DAG, Subtarget);
if (!NewValue)
return SDValue();

if (!InputRootReplacement) {
assert(Res.Root == N &&
"First element is expected to be the current node");
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
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Expand Up @@ -869,12 +869,9 @@ define <4 x i64> @crash(<4 x i16> %x, <4 x i16> %y) {
; CHECK-LABEL: crash:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vsext.vf4 v8, v11
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v11, v10
; CHECK-NEXT: vwaddu.wv v8, v8, v11
; CHECK-NEXT: vsext.vf4 v10, v8
; CHECK-NEXT: vzext.vf4 v12, v9
; CHECK-NEXT: vadd.vv v8, v10, v12
; CHECK-NEXT: ret
%a = sext <4 x i16> %x to <4 x i64>
%b = zext <4 x i16> %y to <4 x i64>
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
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Expand Up @@ -716,10 +716,10 @@ define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) {
;
; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
; CHECK-ZVBB-NEXT: ret
%x = zext <4 x i8> %a to <4 x i64>
%y = zext <4 x i8> %b to <4 x i64>
Expand Down Expand Up @@ -917,9 +917,9 @@ define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {
;
; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2
; CHECK-ZVBB-NEXT: ret
%x = zext <4 x i8> %a to <4 x i64>
%z = shl <4 x i64> %x, splat (i64 2)
Expand Down
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