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Merged
merged 1 commit into from
Sep 23, 2025
Merged

[Hexagon] Generate signed mask for vshuff/vdeal #159800

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9 changes: 8 additions & 1 deletion llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
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Expand Up @@ -2483,8 +2483,15 @@ OpRef HvxSelector::perfect(ShuffleMask SM, OpRef Va, ResultStack &Results) {
}
++I;

// Upper bits of the vdeal/vshuff parameter that do not cover any byte in
// the vector are ignored. Technically, A2_tfrsi takes a signed value, which
// is sign-extended to 32 bit if there is no extender. The practical
// advantages are that signed values are smaller in common use cases and are
// not sensitive to the vector size.
int SS = SignExtend32(S, HwLog);

NodeTemplate Res;
Results.push(Hexagon::A2_tfrsi, MVT::i32, {getConst32(S, dl)});
Results.push(Hexagon::A2_tfrsi, MVT::i32, {getSignedConst32(SS, dl)});
Res.Opc = IsInc ? Hexagon::V6_vshuffvdd : Hexagon::V6_vdealvdd;
Res.Ty = PairTy;
Res.Ops = {OpRef::hi(Arg), OpRef::lo(Arg), OpRef::res(-1)};
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128 changes: 64 additions & 64 deletions llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll
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64 changes: 32 additions & 32 deletions llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll
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Expand Up @@ -6,9 +6,9 @@
; was missing).

; CHECK-LABEL: f0:
; CHECK-DAG: r[[R0:[0-9]+]] = #66
; CHECK-DAG: r[[R0:[0-9]+]] = #-62
; CHECK-DAG: r[[R1:[0-9]+]] = #40
; CHECK-DAG: r[[R2:[0-9]+]] = #85
; CHECK-DAG: r[[R2:[0-9]+]] = #-43
; CHECK: v1:0 = vdeal(v{{[0-9]+}},v0,r[[R0]])
; CHECK: v1:0 = vshuff(v1,v0,r[[R1]])
; CHECK: v1:0 = vshuff(v1,v0,r[[R2]])
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
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Expand Up @@ -5,7 +5,7 @@ define void @f0(ptr %a0, ptr %a1, ptr %a2) #0 {
; CHECK-LABEL: f0:
; CHECK: // %bb.0: // %b0
; CHECK-NEXT: {
; CHECK-NEXT: r7 = #124
; CHECK-NEXT: r7 = #-4
; CHECK-NEXT: v0 = vmem(r0+#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
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Expand Up @@ -10,7 +10,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
; V60-NEXT: v1:0.w = vmpy(v1.h,v0.h)
; V60-NEXT: }
; V60-NEXT: {
; V60-NEXT: r7 = #124
; V60-NEXT: r7 = #-4
; V60-NEXT: }
; V60-NEXT: {
; V60-NEXT: v1:0 = vshuff(v1,v0,r7)
Expand All @@ -28,7 +28,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
; V65-NEXT: v1:0.w = vmpy(v1.h,v0.h)
; V65-NEXT: }
; V65-NEXT: {
; V65-NEXT: r7 = #124
; V65-NEXT: r7 = #-4
; V65-NEXT: }
; V65-NEXT: {
; V65-NEXT: v1:0 = vshuff(v1,v0,r7)
Expand All @@ -46,7 +46,7 @@ define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 {
; V69-NEXT: v1:0.w = vmpy(v1.h,v0.h)
; V69-NEXT: }
; V69-NEXT: {
; V69-NEXT: r7 = #124
; V69-NEXT: r7 = #-4
; V69-NEXT: }
; V69-NEXT: {
; V69-NEXT: v1:0 = vshuff(v1,v0,r7)
Expand All @@ -72,7 +72,7 @@ define <64 x i16> @mulhu16(<64 x i16> %a0, <64 x i16> %a1) #0 {
; V60-NEXT: v1:0.uw = vmpy(v1.uh,v0.uh)
; V60-NEXT: }
; V60-NEXT: {
; V60-NEXT: r7 = #124
; V60-NEXT: r7 = #-4
; V60-NEXT: }
; V60-NEXT: {
; V60-NEXT: v1:0 = vshuff(v1,v0,r7)
Expand All @@ -90,7 +90,7 @@ define <64 x i16> @mulhu16(<64 x i16> %a0, <64 x i16> %a1) #0 {
; V65-NEXT: v1:0.uw = vmpy(v1.uh,v0.uh)
; V65-NEXT: }
; V65-NEXT: {
; V65-NEXT: r7 = #124
; V65-NEXT: r7 = #-4
; V65-NEXT: }
; V65-NEXT: {
; V65-NEXT: v1:0 = vshuff(v1,v0,r7)
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
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Expand Up @@ -75,7 +75,7 @@ define void @f2(ptr %a0, ptr %a1, ptr %a2) #0 {
; CHECK-NEXT: v0 = vmem(r1+#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r7 = #124
; CHECK-NEXT: r7 = #-4
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r3 = #15
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128 changes: 64 additions & 64 deletions llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll
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64 changes: 32 additions & 32 deletions llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll
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30 changes: 15 additions & 15 deletions llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll
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Expand Up @@ -2,7 +2,7 @@

; Generator: vdeal(0x37), vdeal(0x53), vshuff(0x2f), vdeal(0x4b), vdeal(0x27), vdeal(0x43), vshuff(0x1f), vdeal(0x5b), vshuff(0x7e), vshuff(0x6c), vdeal(0x5a), vdeal(0x38), vshuff(0x16), vshuff(0x44), vdeal(0x72)
; CHECK-LABEL: test_0000:
; CHECK-DAG: [[R00:r[0-9]+]] = #66
; CHECK-DAG: [[R00:r[0-9]+]] = #-62
; CHECK-DAG: [[R01:r[0-9]+]] = #46
; CHECK-DAG: [[R02:r[0-9]+]] = #1
; CHECK: v[[H00:[0-9]+]]:[[L00:[0-9]+]] = vshuff(v1,v0,[[R00]])
Expand All @@ -18,7 +18,7 @@ define <256 x i8> @test_0000(<256 x i8> %v0) #0 {
; CHECK-LABEL: test_0001:
; CHECK-DAG: [[R10:r[0-9]+]] = #24
; CHECK-DAG: [[R11:r[0-9]+]] = #9
; CHECK-DAG: [[R12:r[0-9]+]] = #68
; CHECK-DAG: [[R12:r[0-9]+]] = #-60
; CHECK-DAG: [[R13:r[0-9]+]] = #34
; CHECK: v[[H10:[0-9]+]]:[[L10:[0-9]+]] = vshuff(v1,v0,[[R10]])
; CHECK: v[[H11:[0-9]+]]:[[L11:[0-9]+]] = vdeal(v[[H10]],v[[L10]],[[R11]])
Expand All @@ -34,7 +34,7 @@ define <256 x i8> @test_0001(<256 x i8> %v0) #0 {
; CHECK-LABEL: test_0002:
; CHECK-DAG: [[R20:r[0-9]+]] = #18
; CHECK-DAG: [[R21:r[0-9]+]] = #10
; CHECK-DAG: [[R22:r[0-9]+]] = #68
; CHECK-DAG: [[R22:r[0-9]+]] = #-60
; CHECK-DAG: [[R23:r[0-9]+]] = #5
; CHECK: v[[H20:[0-9]+]]:[[L20:[0-9]+]] = vshuff(v1,v0,[[R20]])
; CHECK: v[[H21:[0-9]+]]:[[L21:[0-9]+]] = vdeal(v[[H20]],v[[L20]],[[R21]])
Expand All @@ -51,7 +51,7 @@ define <256 x i8> @test_0002(<256 x i8> %v0) #0 {
; CHECK-DAG: [[R30:r[0-9]+]] = #21
; CHECK-DAG: [[R31:r[0-9]+]] = #9
; CHECK-DAG: [[R32:r[0-9]+]] = #34
; CHECK-DAG: [[R33:r[0-9]+]] = #66
; CHECK-DAG: [[R33:r[0-9]+]] = #-62
; CHECK: v[[H30:[0-9]+]]:[[L30:[0-9]+]] = vshuff(v1,v0,[[R30]])
; CHECK: v[[H31:[0-9]+]]:[[L31:[0-9]+]] = vdeal(v[[H30]],v[[L30]],[[R31]])
; CHECK: v[[H32:[0-9]+]]:[[L32:[0-9]+]] = vshuff(v[[H31]],v[[L31]],[[R32]])
Expand All @@ -65,7 +65,7 @@ define <256 x i8> @test_0003(<256 x i8> %v0) #0 {
; Generator: vdeal(0x63), vshuff(0x6f), vdeal(0x77), vshuff(0x75), vdeal(0x3d), vshuff(0x2d), vshuff(0x00), vshuff(0x5c), vdeal(0x04), vshuff(0x79), vshuff(0x21), vdeal(0x7b), vdeal(0x66), vshuff(0x59), vdeal(0x54)
; CHECK-LABEL: test_0004:
; CHECK-DAG: [[R40:r[0-9]+]] = #38
; CHECK-DAG: [[R41:r[0-9]+]] = #72
; CHECK-DAG: [[R41:r[0-9]+]] = #-56
; CHECK-DAG: [[R42:r[0-9]+]] = #18
; CHECK: v[[H40:[0-9]+]]:[[L40:[0-9]+]] = vshuff(v1,v0,[[R40]])
; CHECK: v[[H41:[0-9]+]]:[[L41:[0-9]+]] = vshuff(v[[H40]],v[[L40]],[[R41]])
Expand All @@ -81,7 +81,7 @@ define <256 x i8> @test_0004(<256 x i8> %v0) #0 {
; CHECK-DAG: [[R50:r[0-9]+]] = #9
; CHECK-DAG: [[R51:r[0-9]+]] = #3
; CHECK-DAG: [[R52:r[0-9]+]] = #48
; CHECK-DAG: [[R53:r[0-9]+]] = #68
; CHECK-DAG: [[R53:r[0-9]+]] = #-60
; CHECK: v[[H50:[0-9]+]]:[[L50:[0-9]+]] = vshuff(v1,v0,[[R50]])
; CHECK: v[[H51:[0-9]+]]:[[L51:[0-9]+]] = vdeal(v[[H50]],v[[L50]],[[R51]])
; CHECK: v[[H52:[0-9]+]]:[[L52:[0-9]+]] = vdeal(v[[H51]],v[[L51]],[[R52]])
Expand All @@ -94,7 +94,7 @@ define <256 x i8> @test_0005(<256 x i8> %v0) #0 {

; Generator: vshuff(0x34), vshuff(0x07), vdeal(0x5d), vshuff(0x05), vshuff(0x50), vshuff(0x13), vdeal(0x31), vdeal(0x6e), vdeal(0x0f), vdeal(0x2c), vdeal(0x28), vdeal(0x76), vdeal(0x22), vdeal(0x3a), vdeal(0x51)
; CHECK-LABEL: test_0006:
; CHECK-DAG: [[R60:r[0-9]+]] = #85
; CHECK-DAG: [[R60:r[0-9]+]] = #-43
; CHECK-DAG: [[R61:r[0-9]+]] = #2
; CHECK: v[[H60:[0-9]+]]:[[L60:[0-9]+]] = vdeal(v1,v0,[[R60]])
; CHECK: v[[H61:[0-9]+]]:[[L61:[0-9]+]] = vshuff(v[[H60]],v[[L60]],[[R61]])
Expand All @@ -106,7 +106,7 @@ define <256 x i8> @test_0006(<256 x i8> %v0) #0 {

; Generator: vshuff(0x25), vshuff(0x4c), vshuff(0x72), vdeal(0x70), vshuff(0x3b), vshuff(0x26), vshuff(0x4d), vdeal(0x20), vshuff(0x7f), vdeal(0x6a), vdeal(0x78), vshuff(0x5f), vdeal(0x10), vdeal(0x71), vshuff(0x6d)
; CHECK-LABEL: test_0007:
; CHECK-DAG: [[R70:r[0-9]+]] = #74
; CHECK-DAG: [[R70:r[0-9]+]] = #-54
; CHECK-DAG: [[R71:r[0-9]+]] = #20
; CHECK-DAG: [[R72:r[0-9]+]] = #34
; CHECK: v[[H70:[0-9]+]]:[[L70:[0-9]+]] = vshuff(v1,v0,[[R70]])
Expand All @@ -120,7 +120,7 @@ define <256 x i8> @test_0007(<256 x i8> %v0) #0 {

; Generator: vshuff(0x2e), vshuff(0x40), vdeal(0x35), vdeal(0x3e), vdeal(0x06), vshuff(0x4b), vshuff(0x24), vshuff(0x09), vdeal(0x18), vshuff(0x42), vshuff(0x43), vshuff(0x41), vshuff(0x23), vdeal(0x3f), vdeal(0x39)
; CHECK-LABEL: test_0008:
; CHECK-DAG: [[R80:r[0-9]+]] = #73
; CHECK-DAG: [[R80:r[0-9]+]] = #-55
; CHECK-DAG: [[R81:r[0-9]+]] = #5
; CHECK-DAG: [[R82:r[0-9]+]] = #48
; CHECK-DAG: [[R83:r[0-9]+]] = #2
Expand All @@ -136,7 +136,7 @@ define <256 x i8> @test_0008(<256 x i8> %v0) #0 {

; Generator: vshuff(0x33), vshuff(0x5e), vshuff(0x2a), vdeal(0x2f), vdeal(0x1f), vshuff(0x14), vshuff(0x17), vshuff(0x1b), vdeal(0x1c), vdeal(0x15), vshuff(0x37), vshuff(0x3c), vdeal(0x4e), vdeal(0x7d), vshuff(0x61)
; CHECK-LABEL: test_0009:
; CHECK-DAG: [[R90:r[0-9]+]] = #96
; CHECK-DAG: [[R90:r[0-9]+]] = #-32
; CHECK-DAG: [[R91:r[0-9]+]] = #18
; CHECK-DAG: [[R92:r[0-9]+]] = #5
; CHECK: v[[H90:[0-9]+]]:[[L90:[0-9]+]] = vshuff(v1,v0,[[R90]])
Expand All @@ -152,7 +152,7 @@ define <256 x i8> @test_0009(<256 x i8> %v0) #0 {
; CHECK-LABEL: test_000a:
; CHECK-DAG: [[Ra0:r[0-9]+]] = #44
; CHECK-DAG: [[Ra1:r[0-9]+]] = #6
; CHECK-DAG: [[Ra2:r[0-9]+]] = #80
; CHECK-DAG: [[Ra2:r[0-9]+]] = #-48
; CHECK: v[[Ha0:[0-9]+]]:[[La0:[0-9]+]] = vshuff(v1,v0,[[Ra0]])
; CHECK: v[[Ha1:[0-9]+]]:[[La1:[0-9]+]] = vdeal(v[[Ha0]],v[[La0]],[[Ra1]])
; CHECK: v[[Ha2:[0-9]+]]:[[La2:[0-9]+]] = vshuff(v[[Ha1]],v[[La1]],[[Ra2]])
Expand All @@ -164,7 +164,7 @@ define <256 x i8> @test_000a(<256 x i8> %v0) #0 {

; Generator: vshuff(0x74), vshuff(0x11), vshuff(0x53), vshuff(0x66), vshuff(0x1d), vdeal(0x59), vshuff(0x63), vshuff(0x49), vdeal(0x00), vshuff(0x38), vshuff(0x45), vdeal(0x68), vshuff(0x65), vshuff(0x6e), vdeal(0x62)
; CHECK-LABEL: test_000b:
; CHECK-DAG: [[Rb0:r[0-9]+]] = #68
; CHECK-DAG: [[Rb0:r[0-9]+]] = #-60
; CHECK-DAG: [[Rb1:r[0-9]+]] = #5
; CHECK-DAG: [[Rb2:r[0-9]+]] = #18
; CHECK-DAG: [[Rb3:r[0-9]+]] = #40
Expand All @@ -182,7 +182,7 @@ define <256 x i8> @test_000b(<256 x i8> %v0) #0 {
; CHECK-LABEL: test_000c:
; CHECK-DAG: [[Rc0:r[0-9]+]] = #10
; CHECK-DAG: [[Rc1:r[0-9]+]] = #3
; CHECK-DAG: [[Rc2:r[0-9]+]] = #84
; CHECK-DAG: [[Rc2:r[0-9]+]] = #-44
; CHECK: v[[Hc0:[0-9]+]]:[[Lc0:[0-9]+]] = vshuff(v1,v0,[[Rc0]])
; CHECK: v[[Hc1:[0-9]+]]:[[Lc1:[0-9]+]] = vdeal(v[[Hc0]],v[[Lc0]],[[Rc1]])
; CHECK: v[[Hc2:[0-9]+]]:[[Lc2:[0-9]+]] = vshuff(v[[Hc1]],v[[Lc1]],[[Rc2]])
Expand All @@ -195,7 +195,7 @@ define <256 x i8> @test_000c(<256 x i8> %v0) #0 {
; Generator: vdeal(0x58), vdeal(0x0b), vdeal(0x21), vdeal(0x7f), vshuff(0x6a), vshuff(0x78), vshuff(0x52), vshuff(0x73), vshuff(0x06), vdeal(0x2d), vdeal(0x32), vdeal(0x48), vdeal(0x75), vdeal(0x55), vshuff(0x0e)
; CHECK-LABEL: test_000d:
; CHECK-DAG: [[Rd0:r[0-9]+]] = #36
; CHECK-DAG: [[Rd1:r[0-9]+]] = #80
; CHECK-DAG: [[Rd1:r[0-9]+]] = #-48
; CHECK-DAG: [[Rd2:r[0-9]+]] = #9
; CHECK: v[[Hd0:[0-9]+]]:[[Ld0:[0-9]+]] = vshuff(v1,v0,[[Rd0]])
; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vshuff(v[[Hd0]],v[[Ld0]],[[Rd1]])
Expand All @@ -208,7 +208,7 @@ define <256 x i8> @test_000d(<256 x i8> %v0) #0 {

; Generator: vdeal(0x6f), vdeal(0x13), vdeal(0x07), vdeal(0x56), vshuff(0x2c), vdeal(0x0c), vdeal(0x33), vshuff(0x22), vdeal(0x02), vshuff(0x18), vdeal(0x4d), vshuff(0x51), vshuff(0x3e), vshuff(0x77), vshuff(0x30)
; CHECK-LABEL: test_000e:
; CHECK-DAG: [[Re0:r[0-9]+]] = #65
; CHECK-DAG: [[Re0:r[0-9]+]] = #-63
; CHECK-DAG: [[Re1:r[0-9]+]] = #24
; CHECK-DAG: [[Re2:r[0-9]+]] = #36
; CHECK: v[[He0:[0-9]+]]:[[Le0:[0-9]+]] = vshuff(v1,v0,[[Re0]])
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll
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Expand Up @@ -2,7 +2,7 @@

; Generator: vdeal(0x1f), vshuff(0x32), vshuff(0x24), vshuff(0x26), vshuff(0x08), vdeal(0x3a), vshuff(0x0c), vdeal(0x0e), vdeal(0x30), vdeal(0x22), vdeal(0x14), vdeal(0x36), vdeal(0x18), vdeal(0x0a), vdeal(0x3c)
; CHECK-LABEL: test_0000:
; CHECK-DAG: [[R00:r[0-9]+]] = #49
; CHECK-DAG: [[R00:r[0-9]+]] = #-15
; CHECK-DAG: [[R01:r[0-9]+]] = #3
; CHECK: v[[H00:[0-9]+]]:[[L00:[0-9]+]] = vshuff(v1,v0,[[R00]])
; CHECK: v[[H01:[0-9]+]]:[[L01:[0-9]+]] = vdeal(v[[H00]],v[[L00]],[[R01]])
Expand All @@ -15,7 +15,7 @@ define <128 x i8> @test_0000(<128 x i8> %v0) #0 {
; Generator: vshuff(0x1e), vshuff(0x00), vdeal(0x12), vshuff(0x34), vshuff(0x0b), vshuff(0x2b), vdeal(0x16), vshuff(0x2e), vshuff(0x1a), vdeal(0x28), vshuff(0x2d), vdeal(0x15), vdeal(0x1d), vshuff(0x25), vshuff(0x0d)
; CHECK-LABEL: test_0001:
; CHECK-DAG: [[R10:r[0-9]+]] = #10
; CHECK-DAG: [[R11:r[0-9]+]] = #34
; CHECK-DAG: [[R11:r[0-9]+]] = #-30
; CHECK-DAG: [[R12:r[0-9]+]] = #16
; CHECK: v[[H10:[0-9]+]]:[[L10:[0-9]+]] = vshuff(v1,v0,[[R10]])
; CHECK: v[[H11:[0-9]+]]:[[L11:[0-9]+]] = vshuff(v[[H10]],v[[L10]],[[R11]])
Expand All @@ -41,7 +41,7 @@ define <128 x i8> @test_0002(<128 x i8> %v0) #0 {

; Generator: vshuff(0x11), vshuff(0x2b), vdeal(0x3d), vdeal(0x3e), vshuff(0x02), vdeal(0x1c), vdeal(0x2f), vdeal(0x0f), vshuff(0x36), vshuff(0x38), vdeal(0x35), vshuff(0x1b), vshuff(0x3b), vdeal(0x21), vdeal(0x15)
; CHECK-LABEL: test_0003:
; CHECK-DAG: [[R30:r[0-9]+]] = #34
; CHECK-DAG: [[R30:r[0-9]+]] = #-30
; CHECK-DAG: [[R31:r[0-9]+]] = #10
; CHECK-DAG: [[R32:r[0-9]+]] = #5
; CHECK: v[[H30:[0-9]+]]:[[L30:[0-9]+]] = vshuff(v1,v0,[[R30]])
Expand All @@ -55,7 +55,7 @@ define <128 x i8> @test_0003(<128 x i8> %v0) #0 {

; Generator: vdeal(0x0a), vdeal(0x10), vdeal(0x31), vshuff(0x30), vdeal(0x00), vdeal(0x39), vdeal(0x0e), vshuff(0x37), vshuff(0x17), vshuff(0x06), vshuff(0x07), vshuff(0x09), vshuff(0x3c), vshuff(0x33), vshuff(0x33)
; CHECK-LABEL: test_0004:
; CHECK-DAG: [[R40:r[0-9]+]] = #57
; CHECK-DAG: [[R40:r[0-9]+]] = #-7
; CHECK-DAG: [[R41:r[0-9]+]] = #6
; CHECK-DAG: [[R42:r[0-9]+]] = #1
; CHECK: v[[H40:[0-9]+]]:[[L40:[0-9]+]] = vshuff(v1,v0,[[R40]])
Expand All @@ -69,7 +69,7 @@ define <128 x i8> @test_0004(<128 x i8> %v0) #0 {

; Generator: vdeal(0x1c), vshuff(0x31), vdeal(0x1f), vshuff(0x29), vdeal(0x1a), vshuff(0x2a), vshuff(0x25), vshuff(0x05), vshuff(0x04), vshuff(0x23), vdeal(0x0d), vdeal(0x20), vshuff(0x29), vdeal(0x2f), vshuff(0x1d)
; CHECK-LABEL: test_0005:
; CHECK-DAG: [[R50:r[0-9]+]] = #33
; CHECK-DAG: [[R50:r[0-9]+]] = #-31
; CHECK-DAG: [[R51:r[0-9]+]] = #12
; CHECK-DAG: [[R52:r[0-9]+]] = #1{{$}}
; CHECK: v[[H50:[0-9]+]]:[[L50:[0-9]+]] = vshuff(v1,v0,[[R50]])
Expand All @@ -84,7 +84,7 @@ define <128 x i8> @test_0005(<128 x i8> %v0) #0 {
; Generator: vdeal(0x22), vshuff(0x24), vdeal(0x16), vdeal(0x18), vshuff(0x17), vdeal(0x2d), vshuff(0x38), vshuff(0x20), vshuff(0x37), vdeal(0x3f), vdeal(0x10), vdeal(0x32), vshuff(0x14), vshuff(0x13), vdeal(0x0b)
; CHECK-LABEL: test_0006:
; CHECK-DAG: [[R60:r[0-9]+]] = #3{{$}}
; CHECK-DAG: [[R61:r[0-9]+]] = #36
; CHECK-DAG: [[R61:r[0-9]+]] = #-28
; CHECK: v[[H60:[0-9]+]]:[[L60:[0-9]+]] = vdeal(v1,v0,[[R60]])
; CHECK: v[[H61:[0-9]+]]:[[L61:[0-9]+]] = vshuff(v[[H60]],v[[L60]],[[R61]])
; CHECK-NOT: v{{[0-9:]+}} =
Expand All @@ -95,7 +95,7 @@ define <128 x i8> @test_0006(<128 x i8> %v0) #0 {

; Generator: vdeal(0x0f), vdeal(0x01), vshuff(0x3b), vdeal(0x0c), vdeal(0x3f), vdeal(0x26), vshuff(0x28), vdeal(0x3a), vdeal(0x02), vdeal(0x1b), vshuff(0x0e), vdeal(0x03), vshuff(0x3d), vshuff(0x2c), vshuff(0x15)
; CHECK-LABEL: test_0007:
; CHECK-DAG: [[R70:r[0-9]+]] = #50
; CHECK-DAG: [[R70:r[0-9]+]] = #-14
; CHECK-DAG: [[R71:r[0-9]+]] = #5{{$}}
; CHECK-DAG: [[R72:r[0-9]+]] = #8
; CHECK: v[[H70:[0-9]+]]:[[L70:[0-9]+]] = vshuff(v1,v0,[[R70]])
Expand Down Expand Up @@ -124,7 +124,7 @@ define <128 x i8> @test_0008(<128 x i8> %v0) #0 {
; Generator: vshuff(0x1d), vshuff(0x18), vdeal(0x09), vshuff(0x2a), vdeal(0x03), vdeal(0x27), vdeal(0x25), vdeal(0x13), vshuff(0x3a), vshuff(0x19), vshuff(0x06), vshuff(0x0f), vshuff(0x3c), vshuff(0x2e), vshuff(0x36)
; CHECK-LABEL: test_0009:
; CHECK-DAG: [[R90:r[0-9]+]] = #17
; CHECK-DAG: [[R91:r[0-9]+]] = #40
; CHECK-DAG: [[R91:r[0-9]+]] = #-24
; CHECK-DAG: [[R92:r[0-9]+]] = #6
; CHECK: v[[H90:[0-9]+]]:[[L90:[0-9]+]] = vdeal(v1,v0,[[R90]])
; CHECK: v[[H91:[0-9]+]]:[[L91:[0-9]+]] = vshuff(v[[H90]],v[[L90]],[[R91]])
Expand All @@ -137,7 +137,7 @@ define <128 x i8> @test_0009(<128 x i8> %v0) #0 {

; Generator: vdeal(0x05), vshuff(0x10), vdeal(0x0d), vshuff(0x12), vdeal(0x08), vshuff(0x22), vdeal(0x24), vshuff(0x3e), vdeal(0x00), vshuff(0x14), vdeal(0x3b), vdeal(0x33), vshuff(0x2f), vdeal(0x13), vdeal(0x14)
; CHECK-LABEL: test_000a:
; CHECK-DAG: [[Ra0:r[0-9]+]] = #56
; CHECK-DAG: [[Ra0:r[0-9]+]] = #-8
; CHECK-DAG: [[Ra1:r[0-9]+]] = #13
; CHECK-DAG: [[Ra2:r[0-9]+]] = #2
; CHECK: v[[Ha0:[0-9]+]]:[[La0:[0-9]+]] = vshuff(v1,v0,[[Ra0]])
Expand All @@ -152,7 +152,7 @@ define <128 x i8> @test_000a(<128 x i8> %v0) #0 {
; Generator: vdeal(0x12), vshuff(0x2c), vdeal(0x2d), vshuff(0x01), vshuff(0x1f), vshuff(0x30), vdeal(0x2a), vdeal(0x0b), vdeal(0x32), vshuff(0x08), vdeal(0x1b), vdeal(0x09), vshuff(0x1c), vshuff(0x16), vdeal(0x38)
; CHECK-LABEL: test_000b:
; CHECK-DAG: [[Rb0:r[0-9]+]] = #12
; CHECK-DAG: [[Rb1:r[0-9]+]] = #33
; CHECK-DAG: [[Rb1:r[0-9]+]] = #-31
; CHECK-DAG: [[Rb2:r[0-9]+]] = #18
; CHECK: v[[Hb0:[0-9]+]]:[[Lb0:[0-9]+]] = vdeal(v1,v0,[[Rb0]])
; CHECK: v[[Hb1:[0-9]+]]:[[Lb1:[0-9]+]] = vdeal(v[[Hb0]],v[[Lb0]],[[Rb1]])
Expand All @@ -168,7 +168,7 @@ define <128 x i8> @test_000b(<128 x i8> %v0) #0 {
; CHECK-DAG: [[Rc0:r[0-9]+]] = #12
; CHECK-DAG: [[Rc1:r[0-9]+]] = #6
; CHECK-DAG: [[Rc2:r[0-9]+]] = #17
; CHECK-DAG: [[Rc3:r[0-9]+]] = #32
; CHECK-DAG: [[Rc3:r[0-9]+]] = #-32
; CHECK: v[[Hc0:[0-9]+]]:[[Lc0:[0-9]+]] = vshuff(v1,v0,[[Rc0]])
; CHECK: v[[Hc1:[0-9]+]]:[[Lc1:[0-9]+]] = vdeal(v[[Hc0]],v[[Lc0]],[[Rc1]])
; CHECK: v[[Hc2:[0-9]+]]:[[Lc2:[0-9]+]] = vdeal(v[[Hc1]],v[[Lc1]],[[Rc2]])
Expand All @@ -181,7 +181,7 @@ define <128 x i8> @test_000c(<128 x i8> %v0) #0 {

; Generator: vdeal(0x3c), vdeal(0x24), vdeal(0x05), vdeal(0x37), vshuff(0x21), vdeal(0x11), vdeal(0x1d), vshuff(0x00), vshuff(0x34), vshuff(0x0d), vshuff(0x3a), vshuff(0x1f), vshuff(0x03), vshuff(0x1e), vdeal(0x29)
; CHECK-LABEL: test_000d:
; CHECK-DAG: [[Rd0:r[0-9]+]] = #40
; CHECK-DAG: [[Rd0:r[0-9]+]] = #-24
; CHECK-DAG: [[Rd1:r[0-9]+]] = #28
; CHECK: v[[Hd0:[0-9]+]]:[[Ld0:[0-9]+]] = vshuff(v1,v0,[[Rd0]])
; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vdeal(v[[Hd0]],v[[Ld0]],[[Rd1]])
Expand All @@ -193,7 +193,7 @@ define <128 x i8> @test_000d(<128 x i8> %v0) #0 {

; Generator: vshuff(0x18), vdeal(0x36), vdeal(0x33), vdeal(0x26), vshuff(0x04), vshuff(0x2d), vshuff(0x35), vdeal(0x34), vdeal(0x2e), vdeal(0x25), vdeal(0x28), vshuff(0x0c), vdeal(0x07), vshuff(0x35), vshuff(0x01)
; CHECK-LABEL: test_000e:
; CHECK-DAG: [[Re0:r[0-9]+]] = #58
; CHECK-DAG: [[Re0:r[0-9]+]] = #-6
; CHECK: v[[He0:[0-9]+]]:[[Le0:[0-9]+]] = vshuff(v1,v0,[[Re0]])
; CHECK-NOT: v{{[0-9:]+}} =
define <128 x i8> @test_000e(<128 x i8> %v0) #0 {
Expand All @@ -203,7 +203,7 @@ define <128 x i8> @test_000e(<128 x i8> %v0) #0 {

; Generator: vshuff(0x1a), vshuff(0x10), vdeal(0x2b), vshuff(0x15), vdeal(0x12), vdeal(0x30), vshuff(0x23), vshuff(0x02), vshuff(0x32), vshuff(0x08), vshuff(0x05), vdeal(0x3e), vshuff(0x39), vshuff(0x0a), vshuff(0x0e)
; CHECK-LABEL: test_000f:
; CHECK-DAG: [[Rf0:r[0-9]+]] = #44
; CHECK-DAG: [[Rf0:r[0-9]+]] = #-20
; CHECK-DAG: [[Rf1:r[0-9]+]] = #18
; CHECK: v[[Hf0:[0-9]+]]:[[Lf0:[0-9]+]] = vshuff(v1,v0,[[Rf0]])
; CHECK: v[[Hf1:[0-9]+]]:[[Lf1:[0-9]+]] = vshuff(v[[Hf0]],v[[Lf0]],[[Rf1]])
Expand Down
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