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[AArch64] Add missing bitcast patterns for bf16<->f16 converts. #159816

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Merged
merged 1 commit into from
Sep 29, 2025
Merged

[AArch64] Add missing bitcast patterns for bf16<->f16 converts. #159816

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20 changes: 16 additions & 4 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -9857,8 +9857,14 @@ def : Pat<(v4bf16 (bitconvert (v2f32 FPR64:$src))),
def : Pat<(v4bf16 (bitconvert (v1f64 FPR64:$src))),
(v4bf16 (REV64v4i16 FPR64:$src))>;
}
def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
def : Pat<(v4bf16 (bitconvert (v4i16 FPR64:$src))), (v4bf16 FPR64:$src)>;
def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
(v4f16 FPR64:$src)>;
def : Pat<(v4f16 (bitconvert (v4bf16 FPR64:$src))),
(v4f16 FPR64:$src)>;
def : Pat<(v4bf16 (bitconvert (v4i16 FPR64:$src))),
(v4bf16 FPR64:$src)>;
def : Pat<(v4bf16 (bitconvert (v4f16 FPR64:$src))),
(v4bf16 FPR64:$src)>;

let Predicates = [IsLE] in {
def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
Expand Down Expand Up @@ -10187,8 +10193,14 @@ def : Pat<(v8bf16 (bitconvert (v2f64 FPR128:$src))),
def : Pat<(v8bf16 (bitconvert (v4f32 FPR128:$src))),
(v8bf16 (REV32v8i16 FPR128:$src))>;
}
def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
def : Pat<(v8bf16 (bitconvert (v8i16 FPR128:$src))), (v8bf16 FPR128:$src)>;
def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
(v8f16 FPR128:$src)>;
def : Pat<(v8bf16 (bitconvert (v8i16 FPR128:$src))),
(v8bf16 FPR128:$src)>;
def : Pat<(v8f16 (bitconvert (v8bf16 FPR128:$src))),
(v8f16 FPR128:$src)>;
def : Pat<(v8bf16 (bitconvert (v8f16 FPR128:$src))),
(v8bf16 FPR128:$src)>;

let Predicates = [IsLE] in {
def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
Expand Down
40 changes: 40 additions & 0 deletions llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,16 @@ entry:
ret <4 x i16> %1
}

define <4 x half> @v4bf16_to_v4f16(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v4f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <4 x half>
ret <4 x half> %1
}

define <2 x i32> @v4bf16_to_v2i32(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v2i32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -82,6 +92,16 @@ entry:
ret <4 x bfloat> %1
}

define <4 x bfloat> @v4f16_to_v4bf16(float, <4 x half> %a) nounwind {
; CHECK-LABEL: v4f16_to_v4bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <4 x bfloat>
ret <4 x bfloat> %1
}

define <4 x bfloat> @v2i32_to_v4bf16(float, <2 x i32> %a) nounwind {
; CHECK-LABEL: v2i32_to_v4bf16:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -152,6 +172,16 @@ entry:
ret <8 x i16> %1
}

define <8 x half> @v8bf16_to_v8f16(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v8f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <8 x half>
ret <8 x half> %1
}

define <4 x i32> @v8bf16_to_v4i32(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v4i32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -202,6 +232,16 @@ entry:
ret <8 x bfloat> %1
}

define <8 x bfloat> @v8f16_to_v8bf16(float, <8 x half> %a) nounwind {
; CHECK-LABEL: v8f16_to_v8bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <8 x bfloat>
ret <8 x bfloat> %1
}

define <8 x bfloat> @v4i32_to_v8bf16(float, <4 x i32> %a) nounwind {
; CHECK-LABEL: v4i32_to_v8bf16:
; CHECK: // %bb.0: // %entry
Expand Down