Skip to content

[AMDGPU] Support xor cond, -1 when lowering BRCOND #160341

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Sep 23, 2025
Merged

[AMDGPU] Support xor cond, -1 when lowering BRCOND #160341

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
2c936fd
[AMDGPU] Support `xor cond, -1` when lowering `BRCOND`
shiltian Sep 23, 2025
8aa4395
assume canonical form
shiltian Sep 23, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
19 changes: 16 additions & 3 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7540,17 +7540,30 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, SelectionDAG &DAG) const {
SDNode *BR = nullptr;
SDNode *SetCC = nullptr;

if (Intr->getOpcode() == ISD::SETCC) {
switch (Intr->getOpcode()) {
case ISD::SETCC: {
// As long as we negate the condition everything is fine
SetCC = Intr;
Intr = SetCC->getOperand(0).getNode();

} else {
break;
}
case ISD::XOR: {
// Similar to SETCC, if we have (xor c, -1), we will be fine.
SDValue LHS = Intr->getOperand(0);
SDValue RHS = Intr->getOperand(1);
if (auto *C = dyn_cast<ConstantSDNode>(RHS); C && C->getZExtValue()) {
Intr = LHS.getNode();
break;
}
[[fallthrough]];
}
default: {
// Get the target from BR if we don't negate the condition
BR = findUser(BRCOND, ISD::BR);
assert(BR && "brcond missing unconditional branch user");
Target = BR->getOperand(1);
}
}

unsigned CFNode = isCFIntrinsic(Intr);
if (CFNode == 0) {
Expand Down
23 changes: 23 additions & 0 deletions llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a --debug-counter=dagcombine=0 -start-before=si-annotate-control-flow %s -o - | FileCheck %s
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Does this require asserts? Does optnone work as well?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This doesn't seem like that, since I didn't receive any emails about test failure. Lol.

optnone doesn't work as well, because even with optnone, some combines can still happen, including this one.


define amdgpu_kernel void @test(i32 %N, ptr addrspace(1) %p) {
; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; CHECK-NEXT: v_cmp_gt_i32_e32 vcc, 1, v0
; CHECK-NEXT: s_and_saveexec_b64 s[0:1], vcc
; CHECK-NEXT: s_endpgm
entry:
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%cmp2 = icmp slt i32 %id.x, 1
br i1 %cmp2, label %if.then, label %exit

if.then:
%idx.ext = zext i32 %N to i64
%add.ptr = getelementptr i8, ptr addrspace(1) %p, i64 %idx.ext
ret void

exit:
ret void
}