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[RISCV][NFC] Rename simm12 to simm12_lo #160380

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Merged
merged 2 commits into from
Sep 23, 2025
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[RISCV][NFC] Rename simm12 to simm12_lo #160380

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2520f7a
[RISCV][NFC] Rename simm12 to simm12_lo
lenary Sep 19, 2025
dde70ac
Merge remote-tracking branch 'origin/main' into pr/riscv-simm12-lo
lenary Sep 23, 2025
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6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -811,6 +811,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isSImm6() const { return isSImm<6>(); }
bool isSImm10() const { return isSImm<10>(); }
bool isSImm11() const { return isSImm<11>(); }
bool isSImm12() const { return isSImm<12>(); }
bool isSImm16() const { return isSImm<16>(); }
bool isSImm26() const { return isSImm<26>(); }

Expand Down Expand Up @@ -859,7 +860,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return SignExtend64<32>(Imm);
}

bool isSImm12() const {
bool isSImm12LO() const {
if (!isExpr())
return false;

Expand Down Expand Up @@ -1599,6 +1600,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidUImm16NonZero:
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16) - 1);
case Match_InvalidSImm12:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 11),
(1 << 11) - 1);
case Match_InvalidSImm12LO:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
"operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an "
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -41,12 +41,12 @@ def GIImmPlus1 :
def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;

// Define pattern expansions for pointer ult/slt conditional codes
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
(SLTIU GPR:$rs1, simm12:$imm12)>;
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12_lo:$imm12)),
(SLTIU GPR:$rs1, simm12_lo:$imm12)>;
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
(SLTU GPR:$rs1, GPR:$rs2)>;
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
(SLTI GPR:$rs1, simm12:$imm12)>;
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12_lo:$imm12)),
(SLTI GPR:$rs1, simm12_lo:$imm12)>;
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
(SLT GPR:$rs1, GPR:$rs2)>;

Expand All @@ -72,12 +72,12 @@ def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty simm12Minus1Nonzero:$imm))),
(XORI (SLTI GPR:$rs1, (ImmPlus1 simm12Minus1Nonzero:$imm)), 1)>;
def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty GPR:$rs2))),
(SLT GPR:$rs2, GPR:$rs1)>;
def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12:$imm))),
(XORI (SLTIU GPR:$rs1, simm12:$imm), 1)>;
def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12_lo:$imm))),
(XORI (SLTIU GPR:$rs1, simm12_lo:$imm), 1)>;
def : Pat<(XLenVT (setuge (Ty GPR:$rs1), (Ty GPR:$rs2))),
(XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12:$imm))),
(XORI (SLTI GPR:$rs1, simm12:$imm), 1)>;
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12_lo:$imm))),
(XORI (SLTI GPR:$rs1, simm12_lo:$imm), 1)>;
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty GPR:$rs2))),
(XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(XLenVT (setule (Ty GPR:$rs1), (Ty simm12Minus1NonzeroNonNeg1:$imm))),
Expand Down Expand Up @@ -143,8 +143,8 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;

def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
(ADDIW GPR:$rs1, simm12:$imm)>;
def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32),
(ADDIW GPR:$rs1, simm12_lo:$imm)>;

// Use sext if the sign bit of the input is 0.
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
Expand Down
102 changes: 52 additions & 50 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoD.td
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Expand Up @@ -529,11 +529,11 @@ def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;

/// Loads
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12_lo:$imm12), []>;

/// Stores
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12_lo:$imm12), []>;
} // Predicates = [HasStdExtZdinx, IsRV32]

let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoF.td
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Expand Up @@ -196,15 +196,15 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class FPLoad_r<bits<3> funct3, string opcodestr, DAGOperand rty,
SchedWrite sw>
: RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd),
(ins GPRMem:$rs1, simm12:$imm12),
(ins GPRMem:$rs1, simm12_lo:$imm12),
opcodestr, "$rd, ${imm12}(${rs1})">,
Sched<[sw, ReadFMemBase]>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class FPStore_r<bits<3> funct3, string opcodestr, DAGOperand rty,
SchedWrite sw>
: RVInstS<funct3, OPC_STORE_FP, (outs),
(ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
(ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
opcodestr, "$rs2, ${imm12}(${rs1})">,
Sched<[sw, ReadFStoreData, ReadFMemBase]>;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
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Expand Up @@ -60,7 +60,7 @@ class SFBALU_rr
class SFBALU_ri
: Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
simm12:$imm), []>,
simm12_lo:$imm), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> {
let hasSideEffects = 0;
let mayLoad = 0;
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Expand Up @@ -271,7 +271,7 @@ class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
(ins GPRMem:$rs1, simm12:$imm12),
(ins GPRMem:$rs1, simm12_lo:$imm12),
opcodestr, "$rd, (${rs1}), ${imm12}"> {
let Constraints = "$rs1_wb = $rs1";
}
Expand All @@ -292,7 +292,7 @@ class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
class CVStore_ri_inc<bits<3> funct3, string opcodestr>
: RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
(ins GPR:$rs2, GPR:$rs1, simm12_lo:$imm12),
opcodestr, "$rs2, (${rs1}), ${imm12}"> {
let Constraints = "$rs1_wb = $rs1";
}
Expand Down Expand Up @@ -332,7 +332,7 @@ class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>

class CVLoad_ri<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
(ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;

//===----------------------------------------------------------------------===//
// Instructions
Expand Down Expand Up @@ -673,8 +673,8 @@ class CVLdrrPat<PatFrag LoadOp, RVInst Inst>
(Inst CVrr:$regreg)>;

class CVStriPat<PatFrag StoreOp, RVInst Inst>
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12:$imm12),
(Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12_lo:$imm12),
(Inst GPR:$rs2, GPR:$rs1, simm12_lo:$imm12)>;

class CVStrriPat<PatFrag StoreOp, RVInst Inst>
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3),
Expand Down
72 changes: 36 additions & 36 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
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Expand Up @@ -953,7 +953,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
}

def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12),
"qc.muliadd", "$rd, $rs1, $imm12"> {
let Constraints = "$rd = $rd_wb";
}
Expand Down Expand Up @@ -1411,8 +1411,8 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
(IntCCtoRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;

let Predicates = [HasVendorXqciac, IsRV32] in {
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12_lo:$imm12))),
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12)>;
def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)),
(QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)),
Expand Down Expand Up @@ -1667,27 +1667,27 @@ def : CompressPat<(QC_E_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
def : CompressPat<(QC_E_LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
(C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12:$imm12),
(LB GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
(LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12:$imm12),
(LH GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
(LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12:$imm12),
(LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
(LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
(LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
(LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
(LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
(LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;

def : CompressPat<(QC_E_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
(C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
def : CompressPat<(QC_E_SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
(C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
(SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
(SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
(SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
(SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
(SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
} // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32]

let Predicates = [HasVendorXqcicm, IsRV32] in {
Expand Down Expand Up @@ -1752,23 +1752,23 @@ def : CompressPat<(QC_E_ADDAI X2, simm10_lsb0000nonzero:$imm),
def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;

def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;

def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12:$imm),
(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12:$imm),
(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12:$imm),
(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm),
(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;

def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12_lo:$imm),
(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12_lo:$imm),
(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12_lo:$imm),
(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12_lo:$imm),
(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]

let isCompressOnly = true, Predicates = [HasVendorXqciac, IsRV32] in {
Expand Down