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Remove the uaddo-only specification #160392

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117ef01
usubo
AZero13 Sep 23, 2025
c042e2d
Merge branch 'main' into break
RKSimon Oct 2, 2025
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7 changes: 1 addition & 6 deletions llvm/include/llvm/CodeGen/TargetLowering.h
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Expand Up @@ -3452,19 +3452,14 @@ class LLVM_ABI TargetLoweringBase {
if (isOperationLegal(Opcode, VT))
return true;

// TODO: The default logic is inherited from code in CodeGenPrepare.
// The opcode should not make a difference by default?
if (Opcode != ISD::UADDO)
return false;

// Allow the transform as long as we have an integer type that is not
// obviously illegal and unsupported and if the math result is used
// besides the overflow check. On some targets (e.g. SPARC), it is
// not profitable to form on overflow op if the math result has no
// concrete users.
if (VT.isVector())
return false;
return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT));
return MathUsed && (isTypeLegal(VT) || !isOperationExpand(Opcode, VT));
}

// Return true if it is profitable to use a scalar input to a BUILD_VECTOR
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9 changes: 9 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
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Expand Up @@ -295,6 +295,15 @@ class AMDGPUTargetLowering : public TargetLowering {
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
return true;
}

bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
if (isOperationLegal(Opcode, VT))
return true;

return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT));
}

SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
int &RefinementSteps, bool &UseOneConstNR,
bool Reciprocal) const override;
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1 change: 0 additions & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -641,7 +641,6 @@ class VectorType;

bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
// Using overflow ops for overflow checks only should beneficial on ARM.
return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
}

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5 changes: 1 addition & 4 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -3405,10 +3405,7 @@ bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {

bool X86TargetLowering::shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool) const {
// TODO: Allow vectors?
if (VT.isVector())
return false;
return VT.isSimple() || !isOperationExpand(Opcode, VT);
return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
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Can we drop this override entirely or is the MathUsed hack critical in come way? In which case it needs a decent comment.

}

bool X86TargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/abdu-neg.ll
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Expand Up @@ -355,7 +355,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: cneg x0, x8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
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9 changes: 4 additions & 5 deletions llvm/test/CodeGen/AArch64/arm64-srl-and.ll
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Expand Up @@ -9,13 +9,12 @@ define i32 @srl_and() {
; CHECK-LABEL: srl_and:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:g
; CHECK-NEXT: mov w9, #50
; CHECK-NEXT: ldr x8, [x8, :got_lo12:g]
; CHECK-NEXT: ldrh w8, [x8]
; CHECK-NEXT: eor w8, w8, w9
; CHECK-NEXT: mov w9, #65535
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: and w0, w8, w8, lsr #16
; CHECK-NEXT: cmp w8, #50
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr @g, align 4
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16 changes: 10 additions & 6 deletions llvm/test/CodeGen/AArch64/atomicrmw-uinc-udec-wrap.ll
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Expand Up @@ -113,10 +113,12 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
; CHECK-NEXT: .LBB6_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxr w8, [x0]
; CHECK-NEXT: subs w9, w8, #1
; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: cmp w8, w1
; CHECK-NEXT: sub w9, w8, #1
; CHECK-NEXT: ccmp w8, #0, #4, ls
; CHECK-NEXT: csel w9, w1, w9, eq
; CHECK-NEXT: csinc w10, w10, wzr, ls
; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel w9, w1, w9, ne
; CHECK-NEXT: stlxr w10, w9, [x0]
; CHECK-NEXT: cbnz w10, .LBB6_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
Expand All @@ -133,10 +135,12 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
; CHECK-NEXT: .LBB7_1: // %atomicrmw.start
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldaxr x0, [x8]
; CHECK-NEXT: subs x9, x0, #1
; CHECK-NEXT: cset w10, lo
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: sub x9, x0, #1
; CHECK-NEXT: ccmp x0, #0, #4, ls
; CHECK-NEXT: csel x9, x1, x9, eq
; CHECK-NEXT: csinc w10, w10, wzr, ls
; CHECK-NEXT: cmp w10, #0
; CHECK-NEXT: csel x9, x1, x9, ne
; CHECK-NEXT: stlxr w10, x9, [x8]
; CHECK-NEXT: cbnz w10, .LBB7_1
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
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8 changes: 3 additions & 5 deletions llvm/test/CodeGen/AArch64/cgp-usubo.ll
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Expand Up @@ -108,11 +108,9 @@ define i1 @usubo_ugt_constant_op1_i8(i8 %x, ptr %p) nounwind {
define i1 @usubo_eq_constant1_op1_i32(i32 %x, ptr %p) nounwind {
; CHECK-LABEL: usubo_eq_constant1_op1_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: sub w9, w0, #1
; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: str w9, [x1]
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: subs w8, w0, #1
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: str w8, [x1]
; CHECK-NEXT: ret
%s = add i32 %x, -1
%ov = icmp eq i32 %x, 0
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
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Expand Up @@ -192,12 +192,12 @@ define i1 @test_conditional2(i32 %a, i32 %b, ptr %c) {
; CHECK-NEXT: mov w22, #2 ; =0x2
; CHECK-NEXT: LBB3_5: ; %for.cond
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cbz w22, LBB3_8
; CHECK-NEXT: subs w22, w22, #1
; CHECK-NEXT: b.lo LBB3_8
; CHECK-NEXT: ; %bb.6: ; %for.body
; CHECK-NEXT: ; in Loop: Header=BB3_5 Depth=1
; CHECK-NEXT: sub w22, w22, #1
; CHECK-NEXT: orr w9, w21, w20
; CHECK-NEXT: ldr w10, [x19, w22, sxtw #2]
; CHECK-NEXT: orr w9, w21, w20
; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: b.eq LBB3_5
; CHECK-NEXT: ; %bb.7: ; %if.then
Expand Down Expand Up @@ -238,12 +238,12 @@ define i1 @test_conditional2(i32 %a, i32 %b, ptr %c) {
; OUTLINE-ATOMICS-NEXT: cset w8, eq
; OUTLINE-ATOMICS-NEXT: LBB3_1: ; %for.cond
; OUTLINE-ATOMICS-NEXT: ; =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: cbz w22, LBB3_4
; OUTLINE-ATOMICS-NEXT: subs w22, w22, #1
; OUTLINE-ATOMICS-NEXT: b.lo LBB3_4
; OUTLINE-ATOMICS-NEXT: ; %bb.2: ; %for.body
; OUTLINE-ATOMICS-NEXT: ; in Loop: Header=BB3_1 Depth=1
; OUTLINE-ATOMICS-NEXT: sub w22, w22, #1
; OUTLINE-ATOMICS-NEXT: orr w9, w21, w20
; OUTLINE-ATOMICS-NEXT: ldr w10, [x19, w22, sxtw #2]
; OUTLINE-ATOMICS-NEXT: orr w9, w21, w20
; OUTLINE-ATOMICS-NEXT: cmp w9, w10
; OUTLINE-ATOMICS-NEXT: b.eq LBB3_1
; OUTLINE-ATOMICS-NEXT: ; %bb.3: ; %if.then
Expand Down
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/AArch64/local-bounds-single-trap.ll
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Expand Up @@ -17,24 +17,22 @@ define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 {
; CHECK-ASM-NEXT: .cfi_remember_state
; CHECK-ASM-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-ASM-NEXT: sxtw x8, w0
; CHECK-ASM-NEXT: mov w9, #10 // =0xa
; CHECK-ASM-NEXT: stp w1, w0, [sp, #8]
; CHECK-ASM-NEXT: cmp x8, #10
; CHECK-ASM-NEXT: b.hi .LBB0_5
; CHECK-ASM-NEXT: subs x9, x9, x8
; CHECK-ASM-NEXT: b.lo .LBB0_5
; CHECK-ASM-NEXT: // %bb.1: // %entry
; CHECK-ASM-NEXT: mov w9, #10 // =0xa
; CHECK-ASM-NEXT: sub x9, x9, x8
; CHECK-ASM-NEXT: cbz x9, .LBB0_5
; CHECK-ASM-NEXT: // %bb.2:
; CHECK-ASM-NEXT: ldrsw x9, [sp, #8]
; CHECK-ASM-NEXT: mov w10, #10 // =0xa
; CHECK-ASM-NEXT: subs x11, x10, x9
; CHECK-ASM-NEXT: adrp x10, .L_MergedGlobals
; CHECK-ASM-NEXT: add x10, x10, :lo12:.L_MergedGlobals
; CHECK-ASM-NEXT: strb wzr, [x10, x8]
; CHECK-ASM-NEXT: cmp x9, #10
; CHECK-ASM-NEXT: b.hi .LBB0_6
; CHECK-ASM-NEXT: b.lo .LBB0_6
; CHECK-ASM-NEXT: // %bb.3:
; CHECK-ASM-NEXT: mov w8, #10 // =0xa
; CHECK-ASM-NEXT: sub x8, x8, x9
; CHECK-ASM-NEXT: cbz x8, .LBB0_6
; CHECK-ASM-NEXT: cbz x11, .LBB0_6
; CHECK-ASM-NEXT: // %bb.4:
; CHECK-ASM-NEXT: add x8, x10, x9
; CHECK-ASM-NEXT: strb wzr, [x8, #10]
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44 changes: 22 additions & 22 deletions llvm/test/CodeGen/AArch64/sat-add.ll
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Expand Up @@ -25,9 +25,9 @@ define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: add w8, w8, #42
; CHECK-NEXT: tst w8, #0x100
; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: add w9, w0, #42
; CHECK-NEXT: cmp w8, w9, uxtb
; CHECK-NEXT: csinv w0, w9, wzr, ls
; CHECK-NEXT: ret
%a = add i8 %x, 42
%c = icmp ugt i8 %x, %a
Expand Down Expand Up @@ -68,9 +68,9 @@ define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: add w8, w8, #42
; CHECK-NEXT: tst w8, #0x10000
; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: add w9, w0, #42
; CHECK-NEXT: cmp w8, w9, uxth
; CHECK-NEXT: csinv w0, w9, wzr, ls
; CHECK-NEXT: ret
%a = add i16 %x, 42
%c = icmp ugt i16 %x, %a
Expand Down Expand Up @@ -188,9 +188,9 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: add w8, w8, w1, uxtb
; CHECK-NEXT: tst w8, #0x100
; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: cmp w8, w9, uxtb
; CHECK-NEXT: csinv w0, w9, wzr, ls
; CHECK-NEXT: ret
%a = add i8 %x, %y
%c = icmp ugt i8 %x, %a
Expand All @@ -201,11 +201,11 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xff
; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: add w8, w8, w0, uxtb
; CHECK-NEXT: tst w8, #0x100
; CHECK-NEXT: csinv w0, w9, wzr, eq
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: mvn w9, w1
; CHECK-NEXT: add w10, w0, w1
; CHECK-NEXT: cmp w8, w9, uxtb
; CHECK-NEXT: csinv w0, w10, wzr, ls
; CHECK-NEXT: ret
%noty = xor i8 %y, -1
%a = add i8 %x, %y
Expand Down Expand Up @@ -234,9 +234,9 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: add w8, w8, w1, uxth
; CHECK-NEXT: tst w8, #0x10000
; CHECK-NEXT: csinv w0, w8, wzr, eq
; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: cmp w8, w9, uxth
; CHECK-NEXT: csinv w0, w9, wzr, ls
; CHECK-NEXT: ret
%a = add i16 %x, %y
%c = icmp ugt i16 %x, %a
Expand All @@ -247,11 +247,11 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w1, #0xffff
; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: add w8, w8, w0, uxth
; CHECK-NEXT: tst w8, #0x10000
; CHECK-NEXT: csinv w0, w9, wzr, eq
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: mvn w9, w1
; CHECK-NEXT: add w10, w0, w1
; CHECK-NEXT: cmp w8, w9, uxth
; CHECK-NEXT: csinv w0, w10, wzr, ls
; CHECK-NEXT: ret
%noty = xor i16 %y, -1
%a = add i16 %x, %y
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/signed-truncation-check.ll
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Expand Up @@ -313,9 +313,9 @@ define i1 @add_ultcmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
define i1 @add_ultcmp_bad_i8_i16(i16 %x) nounwind {
; CHECK-LABEL: add_ultcmp_bad_i8_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: add w8, w8, #128
; CHECK-NEXT: lsr w0, w8, #16
; CHECK-NEXT: add w8, w0, #128
; CHECK-NEXT: tst w8, #0xff80
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ult i16 %tmp0, 128 ; 1U << (8-1)
Expand Down
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