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@zhaoqi5 zhaoqi5 commented Sep 24, 2025

tests for #157824

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llvmbot commented Sep 24, 2025

@llvm/pr-subscribers-backend-loongarch

Author: ZhaoQi (zhaoqi5)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/160480.diff

3 Files Affected:

  • (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+2-4)
  • (added) llvm/test/CodeGen/LoongArch/lasx/scalarize-fp.ll (+84)
  • (added) llvm/test/CodeGen/LoongArch/lsx/scalarize-fp.ll (+73)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 32baa2d111270..d32eb7df866ab 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -1610,11 +1610,9 @@ lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
     return DAG.getUNDEF(VT);
 
   assert(SplatIndex < (int)Mask.size() && "Out of bounds mask index");
-  if (fitsRegularPattern<int>(Mask.begin(), 1, Mask.end(), SplatIndex, 0)) {
-    APInt Imm(64, SplatIndex);
+  if (fitsRegularPattern<int>(Mask.begin(), 1, Mask.end(), SplatIndex, 0))
     return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1,
-                       DAG.getConstant(Imm, DL, Subtarget.getGRLenVT()));
-  }
+                       DAG.getConstant(SplatIndex, DL, Subtarget.getGRLenVT()));
 
   return SDValue();
 }
diff --git a/llvm/test/CodeGen/LoongArch/lasx/scalarize-fp.ll b/llvm/test/CodeGen/LoongArch/lasx/scalarize-fp.ll
new file mode 100644
index 0000000000000..6bd9c9e95f4c3
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/scalarize-fp.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+
+define <8 x float> @fadd_elt0_v8f32(float %a) nounwind {
+; CHECK-LABEL: fadd_elt0_v8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f0 killed $f0 def $xr0
+; CHECK-NEXT:    lu12i.w $a0, 260096
+; CHECK-NEXT:    xvreplgr2vr.w $xr1, $a0
+; CHECK-NEXT:    xvfadd.s $xr0, $xr0, $xr1
+; CHECK-NEXT:    ret
+entry:
+  %b = insertelement <8 x float> poison, float %a, i32 0
+  %c = fadd <8 x float> %b, <float 1.0, float poison, float poison, float poison, float poison, float poison, float poison, float poison>
+  ret <8 x float> %c
+}
+
+define <4 x double> @fadd_elt0_v4f64(double %a) nounwind {
+; LA32-LABEL: fadd_elt0_v4f64:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA32-NEXT:    vldi $vr1, -912
+; LA32-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: fadd_elt0_v4f64:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA64-NEXT:    lu52i.d $a0, $zero, 1023
+; LA64-NEXT:    xvreplgr2vr.d $xr1, $a0
+; LA64-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; LA64-NEXT:    ret
+entry:
+  %b = insertelement <4 x double> poison, double %a, i32 0
+  %c = fadd <4 x double> %b, <double 1.0, double poison, double poison, double poison>
+  ret <4 x double> %c
+}
+
+define <8 x float> @fsub_splat_v8f32(float %a, float %b) nounwind {
+; CHECK-LABEL: fsub_splat_v8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vr1
+; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; CHECK-NEXT:    vfsub.s $vr0, $vr0, $vr1
+; CHECK-NEXT:    xvpermi.d $xr0, $xr0, 68
+; CHECK-NEXT:    xvrepl128vei.w $xr0, $xr0, 0
+; CHECK-NEXT:    ret
+entry:
+  %insa = insertelement <8 x float> poison, float %a, i32 0
+  %insb = insertelement <8 x float> poison, float %b, i32 0
+  %va = shufflevector <8 x float> %insa, <8 x float> poison, <8 x i32> zeroinitializer
+  %vb = shufflevector <8 x float> %insb, <8 x float> poison, <8 x i32> zeroinitializer
+  %c = fsub <8 x float> %va, %vb
+  ret <8 x float> %c
+}
+
+define <4 x double> @fsub_splat_v4f64(double %a) nounwind {
+; LA32-LABEL: fsub_splat_v4f64:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA32-NEXT:    vldi $vr1, -784
+; LA32-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; LA32-NEXT:    xvpermi.d $xr0, $xr0, 68
+; LA32-NEXT:    xvrepl128vei.d $xr0, $xr0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: fsub_splat_v4f64:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $xr0
+; LA64-NEXT:    lu52i.d $a0, $zero, -1025
+; LA64-NEXT:    xvreplgr2vr.d $xr1, $a0
+; LA64-NEXT:    xvfadd.d $xr0, $xr0, $xr1
+; LA64-NEXT:    xvpermi.d $xr0, $xr0, 68
+; LA64-NEXT:    xvrepl128vei.d $xr0, $xr0, 0
+; LA64-NEXT:    ret
+entry:
+  %insa = insertelement <4 x double> poison, double %a, i32 0
+  %insb = insertelement <4 x double> poison, double 1.0, i32 0
+  %va = shufflevector <4 x double> %insa, <4 x double> poison, <4 x i32> zeroinitializer
+  %vb = shufflevector <4 x double> %insb, <4 x double> poison, <4 x i32> zeroinitializer
+  %c = fsub <4 x double> %va, %vb
+  ret <4 x double> %c
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/scalarize-fp.ll b/llvm/test/CodeGen/LoongArch/lsx/scalarize-fp.ll
new file mode 100644
index 0000000000000..cf5cbc3b993c6
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/scalarize-fp.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+
+define <4 x float> @fadd_elt0_v4f32(float %a) nounwind {
+; CHECK-LABEL: fadd_elt0_v4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; CHECK-NEXT:    lu12i.w $a0, 260096
+; CHECK-NEXT:    vreplgr2vr.w $vr1, $a0
+; CHECK-NEXT:    vfadd.s $vr0, $vr0, $vr1
+; CHECK-NEXT:    ret
+entry:
+  %b = insertelement <4 x float> poison, float %a, i32 0
+  %c = fadd <4 x float> %b, <float 1.0, float poison, float poison, float poison>
+  ret <4 x float> %c
+}
+
+define <2 x double> @fadd_elt0_v2f64(double %a) nounwind {
+; LA32-LABEL: fadd_elt0_v2f64:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA32-NEXT:    vldi $vr1, -912
+; LA32-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: fadd_elt0_v2f64:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; LA64-NEXT:    lu52i.d $a0, $zero, 1023
+; LA64-NEXT:    vreplgr2vr.d $vr1, $a0
+; LA64-NEXT:    vfadd.d $vr0, $vr0, $vr1
+; LA64-NEXT:    ret
+entry:
+  %b = insertelement <2 x double> poison, double %a, i32 0
+  %c = fadd <2 x double> %b, <double 1.0, double poison>
+  ret <2 x double> %c
+}
+
+define <4 x float> @fsub_splat_v4f32(float %b) nounwind {
+; CHECK-LABEL: fsub_splat_v4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f0 killed $f0 def $vr0
+; CHECK-NEXT:    lu12i.w $a0, 260096
+; CHECK-NEXT:    vreplgr2vr.w $vr1, $a0
+; CHECK-NEXT:    vfsub.s $vr0, $vr1, $vr0
+; CHECK-NEXT:    vreplvei.w $vr0, $vr0, 0
+; CHECK-NEXT:    ret
+entry:
+  %insa = insertelement <4 x float> poison, float 1.0, i32 0
+  %insb = insertelement <4 x float> poison, float %b, i32 0
+  %va = shufflevector <4 x float> %insa, <4 x float> poison, <4 x i32> zeroinitializer
+  %vb = shufflevector <4 x float> %insb, <4 x float> poison, <4 x i32> zeroinitializer
+  %c = fsub <4 x float> %va, %vb
+  ret <4 x float> %c
+}
+
+define <2 x double> @fsub_splat_v2f64(double %a, double %b) nounwind {
+; CHECK-LABEL: fsub_splat_v2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f1_64 killed $f1_64 def $vr1
+; CHECK-NEXT:    # kill: def $f0_64 killed $f0_64 def $vr0
+; CHECK-NEXT:    vfsub.d $vr0, $vr0, $vr1
+; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 0
+; CHECK-NEXT:    ret
+entry:
+  %insa = insertelement <2 x double> poison, double %a, i32 0
+  %insb = insertelement <2 x double> poison, double %b, i32 0
+  %va = shufflevector <2 x double> %insa, <2 x double> poison, <2 x i32> zeroinitializer
+  %vb = shufflevector <2 x double> %insb, <2 x double> poison, <2 x i32> zeroinitializer
+  %c = fsub <2 x double> %va, %vb
+  ret <2 x double> %c
+}

@zhaoqi5 zhaoqi5 changed the title [LoongArch][NFC] Pre-commit scalarize fp tests and fix for la32 [LoongArch][NFC] Pre-commit scalarize fp tests for #157824 Sep 26, 2025
@zhaoqi5 zhaoqi5 force-pushed the users/zhaoqi5/test-isxxxcheap branch from 1362a74 to 6b0057d Compare September 29, 2025 06:52
@zhaoqi5 zhaoqi5 enabled auto-merge (squash) September 29, 2025 06:53
@zhaoqi5 zhaoqi5 merged commit 3a3a4fb into main Sep 29, 2025
9 checks passed
@zhaoqi5 zhaoqi5 deleted the users/zhaoqi5/test-isxxxcheap branch September 29, 2025 07:27
mahesh-attarde pushed a commit to mahesh-attarde/llvm-project that referenced this pull request Oct 3, 2025
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