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Sep 26, 2025
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[NFC][PowerPC] Consolidate predicate definitions into PPC.td #160579

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fc3e15d
[NFC][PowerPC] Consolidate predicate definitions into PPC.td
lei137 Sep 24, 2025
60a2efc
remove predicate In64BitMode since it's the same as IsPPC64
lei137 Sep 24, 2025
c2411af
apply clang-format
lei137 Sep 24, 2025
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40 changes: 33 additions & 7 deletions llvm/lib/Target/PowerPC/PPC.td
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Expand Up @@ -360,8 +360,11 @@ def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",

//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
def In64BitMode : Predicate<"Subtarget->isPPC64()">;

def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
def IsBookE : Predicate<"Subtarget->isBookE()">;
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
Expand All @@ -379,27 +382,50 @@ def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def HasHTM : Predicate<"Subtarget->hasHTM()">;
def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
def MMA : Predicate<"Subtarget->hasMMA()">;

// Vector support predicates
def HasVSX : Predicate<"Subtarget->hasVSX()">;
def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">;
def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
def NoP10Vector : Predicate<"!Subtarget->hasP10Vector()">;
def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">;

// Predicates used to differenciate between different ISAs.
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;

// AIX assembler may not be modern enough to support some extended mne.
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;

//===----------------------------------------------------------------------===//
// HwModes
//===----------------------------------------------------------------------===//

defvar PPC32 = DefaultMode;
def PPC64 : HwMode<[In64BitMode]>;
def PPC64 : HwMode<[IsPPC64]>;

// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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Expand Up @@ -76,23 +76,23 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(PPCretglue)]>, Requires<[In64BitMode]>;
[(PPCretglue)]>, Requires<[IsPPC64]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
let isPredicable = 1 in
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
[]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;

def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
"bcctr 12, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
"bcctr 4, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}
}

Expand Down Expand Up @@ -160,20 +160,20 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
let isPredicable = 1 in
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl)]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;

let isCodeGenOnly = 1 in {
def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
[]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;

def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
"bcctrl 12, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
"bcctrl 4, $BI, 0", IIC_BrB, []>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}
}
}
Expand Down Expand Up @@ -207,7 +207,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
let isPredicable = 1 in
def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}
}

Expand All @@ -218,7 +218,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
(ins (memrix $D, $RA):$src),
"bctrl\n\tld 2, $src", IIC_BrB,
[(PPCbctrl_load_toc iaddrX4:$src)]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}

let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
Expand All @@ -228,7 +228,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
(ins (memrix $D, $RA):$src),
"bctrl\n\tld 2, $src", IIC_BrB,
[(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}

} // Interpretation64Bit
Expand Down Expand Up @@ -449,7 +449,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;

let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
Expand Down Expand Up @@ -516,15 +516,15 @@ let hasSideEffects = 1 in {
def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP64",
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}

let hasSideEffects = 1, isBarrier = 1 in {
let isTerminator = 1 in
def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
"#EH_SJLJ_LONGJMP64",
[(PPCeh_sjlj_longjmp addr:$buf)]>,
Requires<[In64BitMode]>;
Requires<[IsPPC64]>;
}

def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
Expand Down Expand Up @@ -1948,7 +1948,7 @@ def : Pat<(atomic_load_nonext_64 XForm:$src), (LDX memrr:$src)>;
def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>;
def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>;

let Predicates = [IsISA3_0, In64BitMode] in {
let Predicates = [IsISA3_0, IsPPC64] in {
def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),
(i64 (SETB8 (CMPEQB $a, $b)))>;
def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)),
Expand All @@ -1961,7 +1961,7 @@ def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)),
(i64 (MADDLD8 $a, $b, $c))>;
}

let Predicates = [In64BitMode] in {
let Predicates = [IsPPC64] in {
def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
(i64 (MULHD $a, $b))>;
def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),
Expand Down
4 changes: 0 additions & 4 deletions llvm/lib/Target/PowerPC/PPCInstrAltivec.td
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Expand Up @@ -343,7 +343,6 @@ class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
//===----------------------------------------------------------------------===//
// Instruction Definitions.

def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
let Predicates = [HasAltivec] in {

def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
Expand Down Expand Up @@ -1193,8 +1192,6 @@ class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
let PS = 0;
}

def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
let Predicates = [HasP8Altivec] in {

let isCommutable = 1 in {
Expand Down Expand Up @@ -1420,7 +1417,6 @@ def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
} // HasP8Crypto

// The following altivec instructions were introduced in Power ISA 3.0
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
let Predicates = [HasP9Altivec] in {

// Vector Multiply-Sum
Expand Down
4 changes: 0 additions & 4 deletions llvm/lib/Target/PowerPC/PPCInstrHTM.td
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Expand Up @@ -11,10 +11,6 @@
//
//===----------------------------------------------------------------------===//



def HasHTM : Predicate<"Subtarget->hasHTM()">;

def HTM_get_imm : SDNodeXForm<imm, [{
return getI32Imm (N->getZExtValue(), SDLoc(N));
}]>;
Expand Down
22 changes: 10 additions & 12 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
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Expand Up @@ -1282,7 +1282,7 @@ def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(PPCretglue)]>, Requires<[In32BitMode]>;
[(PPCretglue)]>, Requires<[IsPPC32]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
let isPredicable = 1 in
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
Expand Down Expand Up @@ -1455,7 +1455,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
let isPredicable = 1 in
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl)]>,
Requires<[In32BitMode]>;
Requires<[IsPPC32]>;

let isCodeGenOnly = 1 in {
def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
Expand Down Expand Up @@ -1541,7 +1541,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {
let isPredicable = 1 in
def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
Requires<[In32BitMode]>;
Requires<[IsPPC32]>;
}
}

Expand All @@ -1567,7 +1567,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
def BCTRL_LWZinto_toc:
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[IsPPC32]>;

}

Expand All @@ -1576,7 +1576,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
def BCTRL_LWZinto_toc_RM:
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[IsPPC32]>;

}

Expand All @@ -1585,7 +1585,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>, Requires<[In32BitMode]>;
[]>, Requires<[IsPPC32]>;

let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
Expand All @@ -1608,15 +1608,15 @@ let hasSideEffects = 1 in {
def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP32",
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
Requires<[In32BitMode]>;
Requires<[IsPPC32]>;
}

let hasSideEffects = 1, isBarrier = 1 in {
let isTerminator = 1 in
def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
"#EH_SJLJ_LONGJMP32",
[(PPCeh_sjlj_longjmp addr:$buf)]>,
Requires<[In32BitMode]>;
Requires<[IsPPC32]>;
}

// This pseudo is never removed from the function, as it serves as
Expand Down Expand Up @@ -3438,8 +3438,6 @@ def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;

def MMA : Predicate<"Subtarget->hasMMA()">;

// Prefixed instructions may require access to the above defs at a later
// time so we include this after the def.
include "PPCInstrP10.td"
Expand Down Expand Up @@ -5144,9 +5142,9 @@ def RotateInsertByte1 {
}

// Clear the upper half of the register when in 64-bit mode
let Predicates = [In64BitMode] in
let Predicates = [IsPPC64] in
def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
let Predicates = [In32BitMode] in
let Predicates = [IsPPC32] in
def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;

// Fast 64-bit reverse bits algorithm:
Expand Down
7 changes: 0 additions & 7 deletions llvm/lib/Target/PowerPC/PPCInstrP10.td
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Expand Up @@ -51,10 +51,6 @@
// Moreover, the order of operands reflects the order of operands
// in the encoding.

//-------------------------- Predicate definitions ---------------------------//
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;


//===----------------------------------------------------------------------===//
// PowerPC ISA 3.1 specific type constraints.
//
Expand Down Expand Up @@ -634,9 +630,6 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
}
}

def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
def RCCp {
dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
Expand Down
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