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[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax #160637

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merged 3 commits into from
Oct 3, 2025
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[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax #160637

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9b4a9c6
Fix Issue #160611
ningxinr Sep 25, 2025
f6db9a0
Addressed feedbacks and fixed typos
ningxinr Sep 29, 2025
baf5cde
Added the non sat comment
ningxinr Sep 29, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6046,7 +6046,7 @@ static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
return N02;
}

if (MaxC == 0 && MinCPlus1.isPowerOf2()) {
if (MaxC == 0 && MinC != 0 && MinCPlus1.isPowerOf2()) {
BW = MinCPlus1.exactLogBase2();
Unsigned = true;
return N02;
Expand Down
55 changes: 39 additions & 16 deletions llvm/test/CodeGen/AArch64/fpclamptosat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -111,14 +111,14 @@ entry:
ret i32 %conv6
}

define i32 @utesth_f16i32(half %x) {
; CHECK-CVT-LABEL: utesth_f16i32:
define i32 @utest_f16i32(half %x) {
; CHECK-CVT-LABEL: utest_f16i32:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcvtzu w0, s0
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: utesth_f16i32:
; CHECK-FP16-LABEL: utest_f16i32:
; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: fcvtzu w0, h0
; CHECK-FP16-NEXT: ret
Expand Down Expand Up @@ -298,8 +298,8 @@ entry:
ret i16 %conv6
}

define i16 @utesth_f16i16(half %x) {
; CHECK-CVT-LABEL: utesth_f16i16:
define i16 @utest_f16i16(half %x) {
; CHECK-CVT-LABEL: utest_f16i16:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff
Expand All @@ -308,7 +308,7 @@ define i16 @utesth_f16i16(half %x) {
; CHECK-CVT-NEXT: csel w0, w8, w9, lo
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: utesth_f16i16:
; CHECK-FP16-LABEL: utest_f16i16:
; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: fcvtzu w8, h0
; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff
Expand Down Expand Up @@ -493,8 +493,8 @@ entry:
ret i64 %conv6
}

define i64 @utesth_f16i64(half %x) {
; CHECK-LABEL: utesth_f16i64:
define i64 @utest_f16i64(half %x) {
; CHECK-LABEL: utest_f16i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
Expand Down Expand Up @@ -636,14 +636,14 @@ entry:
ret i32 %conv6
}

define i32 @utesth_f16i32_mm(half %x) {
; CHECK-CVT-LABEL: utesth_f16i32_mm:
define i32 @utest_f16i32_mm(half %x) {
; CHECK-CVT-LABEL: utest_f16i32_mm:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcvtzu w0, s0
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: utesth_f16i32_mm:
; CHECK-FP16-LABEL: utest_f16i32_mm:
; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: fcvtzu w0, h0
; CHECK-FP16-NEXT: ret
Expand Down Expand Up @@ -808,8 +808,8 @@ entry:
ret i16 %conv6
}

define i16 @utesth_f16i16_mm(half %x) {
; CHECK-CVT-LABEL: utesth_f16i16_mm:
define i16 @utest_f16i16_mm(half %x) {
; CHECK-CVT-LABEL: utest_f16i16_mm:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff
Expand All @@ -818,7 +818,7 @@ define i16 @utesth_f16i16_mm(half %x) {
; CHECK-CVT-NEXT: csel w0, w8, w9, lo
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: utesth_f16i16_mm:
; CHECK-FP16-LABEL: utest_f16i16_mm:
; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: fcvtzu w8, h0
; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff
Expand Down Expand Up @@ -986,8 +986,8 @@ entry:
ret i64 %conv6
}

define i64 @utesth_f16i64_mm(half %x) {
; CHECK-LABEL: utesth_f16i64_mm:
define i64 @utest_f16i64_mm(half %x) {
; CHECK-LABEL: utest_f16i64_mm:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
Expand Down Expand Up @@ -1026,6 +1026,29 @@ entry:
ret i64 %conv6
}

; i32 non saturate

define i32 @ustest_f16i32_nsat(half %x) {
; CHECK-CVT-LABEL: ustest_f16i32_nsat:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcvtzs w8, s0
; CHECK-CVT-NEXT: and w8, w8, w8, asr #31
; CHECK-CVT-NEXT: bic w0, w8, w8, asr #31
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: ustest_f16i32_nsat:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: fcvtzs w8, h0
; CHECK-FP16-NEXT: and w8, w8, w8, asr #31
; CHECK-FP16-NEXT: bic w0, w8, w8, asr #31
; CHECK-FP16-NEXT: ret
%conv = fptosi half %x to i32
%spec.store.select = call i32 @llvm.smin.i32(i32 0, i32 %conv)
%spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
ret i32 %spec.store.select7
}

declare i32 @llvm.smin.i32(i32, i32)
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umin.i32(i32, i32)
Expand Down
101 changes: 73 additions & 28 deletions llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -321,20 +321,20 @@ entry:
ret <4 x i32> %conv6
}

define <4 x i32> @utesth_f16i32(<4 x half> %x) {
; CHECK-CVT-SD-LABEL: utesth_f16i32:
define <4 x i32> @utest_f16i32(<4 x half> %x) {
; CHECK-CVT-SD-LABEL: utest_f16i32:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i32:
; CHECK-FP16-SD-LABEL: utest_f16i32:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: utesth_f16i32:
; CHECK-CVT-GI-LABEL: utest_f16i32:
; CHECK-CVT-GI: // %bb.0: // %entry
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
Expand All @@ -349,7 +349,7 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) {
; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i32:
; CHECK-FP16-GI-LABEL: utest_f16i32:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
Expand Down Expand Up @@ -614,8 +614,8 @@ entry:
ret <8 x i16> %conv6
}

define <8 x i16> @utesth_f16i16(<8 x half> %x) {
; CHECK-CVT-LABEL: utesth_f16i16:
define <8 x i16> @utest_f16i16(<8 x half> %x) {
; CHECK-CVT-LABEL: utest_f16i16:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
Expand All @@ -625,12 +625,12 @@ define <8 x i16> @utesth_f16i16(<8 x half> %x) {
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i16:
; CHECK-FP16-SD-LABEL: utest_f16i16:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i16:
; CHECK-FP16-GI-LABEL: utest_f16i16:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
Expand Down Expand Up @@ -1746,8 +1746,8 @@ entry:
ret <2 x i64> %conv6
}

define <2 x i64> @utesth_f16i64(<2 x half> %x) {
; CHECK-CVT-SD-LABEL: utesth_f16i64:
define <2 x i64> @utest_f16i64(<2 x half> %x) {
; CHECK-CVT-SD-LABEL: utest_f16i64:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
Expand Down Expand Up @@ -1777,7 +1777,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: add sp, sp, #48
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i64:
; CHECK-FP16-SD-LABEL: utest_f16i64:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
Expand Down Expand Up @@ -1807,7 +1807,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: add sp, sp, #48
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: utesth_f16i64:
; CHECK-CVT-GI-LABEL: utest_f16i64:
; CHECK-CVT-GI: // %bb.0: // %entry
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
Expand All @@ -1819,7 +1819,7 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) {
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i64:
; CHECK-FP16-GI-LABEL: utest_f16i64:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
Expand Down Expand Up @@ -2307,20 +2307,20 @@ entry:
ret <4 x i32> %conv6
}

define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
; CHECK-CVT-SD-LABEL: utesth_f16i32_mm:
define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
; CHECK-CVT-SD-LABEL: utest_f16i32_mm:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i32_mm:
; CHECK-FP16-SD-LABEL: utest_f16i32_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: utesth_f16i32_mm:
; CHECK-CVT-GI-LABEL: utest_f16i32_mm:
; CHECK-CVT-GI: // %bb.0: // %entry
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
Expand All @@ -2335,7 +2335,7 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i32_mm:
; CHECK-FP16-GI-LABEL: utest_f16i32_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
Expand Down Expand Up @@ -2585,8 +2585,8 @@ entry:
ret <8 x i16> %conv6
}

define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
; CHECK-CVT-LABEL: utesth_f16i16_mm:
define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
; CHECK-CVT-LABEL: utest_f16i16_mm:
; CHECK-CVT: // %bb.0: // %entry
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
Expand All @@ -2596,12 +2596,12 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
; CHECK-FP16-SD-LABEL: utest_f16i16_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i16_mm:
; CHECK-FP16-GI-LABEL: utest_f16i16_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
Expand Down Expand Up @@ -3694,8 +3694,8 @@ entry:
ret <2 x i64> %conv6
}

define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-LABEL: utesth_f16i64_mm:
define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-LABEL: utest_f16i64_mm:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
Expand Down Expand Up @@ -3725,7 +3725,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: add sp, sp, #48
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: utesth_f16i64_mm:
; CHECK-FP16-SD-LABEL: utest_f16i64_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
Expand Down Expand Up @@ -3755,7 +3755,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: add sp, sp, #48
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: utesth_f16i64_mm:
; CHECK-CVT-GI-LABEL: utest_f16i64_mm:
; CHECK-CVT-GI: // %bb.0: // %entry
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
Expand All @@ -3767,7 +3767,7 @@ define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: utesth_f16i64_mm:
; CHECK-FP16-GI-LABEL: utest_f16i64_mm:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
Expand Down Expand Up @@ -3941,6 +3941,51 @@ entry:
ret <2 x i64> %conv6
}

; i32 non saturate

define <4 x i32> @ustest_f16i32_nsat(<4 x half> %x) {
; CHECK-CVT-SD-LABEL: ustest_f16i32_nsat:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-CVT-SD-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: ustest_f16i32_nsat:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-FP16-SD-NEXT: smin v0.4s, v0.4s, v1.4s
; CHECK-FP16-SD-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: ustest_f16i32_nsat:
; CHECK-CVT-GI: // %bb.0: // %entry
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-CVT-GI-NEXT: smin v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: ustest_f16i32_nsat:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
; CHECK-FP16-GI-NEXT: movi v1.2d, #0000000000000000
; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-FP16-GI-NEXT: smin v0.4s, v1.4s, v0.4s
; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i32>
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> zeroinitializer, <4 x i32> %conv)
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
ret <4 x i32> %spec.store.select7
}

declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
Expand Down
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