[RISCV] Add commutative support for Qualcomm uC Xqcicm extension

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1023,6 +1023,37 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
   Cond.push_back(LastInst.getOperand(1));
 }
 
+static unsigned getInverseXqcicmOpcode(unsigned Opcode) {
+  switch (Opcode) {
+  default:
+    llvm_unreachable("Unexpected Opcode");
+  case RISCV::QC_MVEQ:
+    return RISCV::QC_MVNE;
+  case RISCV::QC_MVNE:
+    return RISCV::QC_MVEQ;
+  case RISCV::QC_MVLT:
+    return RISCV::QC_MVGE;
+  case RISCV::QC_MVGE:
+    return RISCV::QC_MVLT;
+  case RISCV::QC_MVLTU:
+    return RISCV::QC_MVGEU;
+  case RISCV::QC_MVGEU:
+    return RISCV::QC_MVLTU;
+  case RISCV::QC_MVEQI:
+    return RISCV::QC_MVNEI;
+  case RISCV::QC_MVNEI:
+    return RISCV::QC_MVEQI;
+  case RISCV::QC_MVLTI:
+    return RISCV::QC_MVGEI;
+  case RISCV::QC_MVGEI:
+    return RISCV::QC_MVLTI;
+  case RISCV::QC_MVLTUI:
+    return RISCV::QC_MVGEUI;
+  case RISCV::QC_MVGEUI:
+    return RISCV::QC_MVLTUI;
+  }
+}
+
 unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
   switch (SelectOpc) {
   default:
@@ -3762,6 +3793,19 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
       return false;
     // Operands 1 and 2 are commutable, if we switch the opcode.
     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+  case RISCV::QC_MVEQ:
+  case RISCV::QC_MVNE:
+  case RISCV::QC_MVLT:
+  case RISCV::QC_MVGE:
+  case RISCV::QC_MVLTU:
+  case RISCV::QC_MVGEU:
+  case RISCV::QC_MVEQI:
+  case RISCV::QC_MVNEI:
+  case RISCV::QC_MVLTI:
+  case RISCV::QC_MVGEI:
+  case RISCV::QC_MVLTUI:
+  case RISCV::QC_MVGEUI:
+    return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
   case RISCV::TH_MULA:
   case RISCV::TH_MULAW:
   case RISCV::TH_MULAH:
@@ -3974,6 +4018,23 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
                                                    OpIdx2);
   }
+  case RISCV::QC_MVEQ:
+  case RISCV::QC_MVNE:
+  case RISCV::QC_MVLT:
+  case RISCV::QC_MVGE:
+  case RISCV::QC_MVLTU:
+  case RISCV::QC_MVGEU:
+  case RISCV::QC_MVEQI:
+  case RISCV::QC_MVNEI:
+  case RISCV::QC_MVLTI:
+  case RISCV::QC_MVGEI:
+  case RISCV::QC_MVLTUI:
+  case RISCV::QC_MVGEUI: {
+    auto &WorkingMI = cloneIfNew(MI);
+    WorkingMI.setDesc(get(getInverseXqcicmOpcode(MI.getOpcode())));
+    return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+                                                   OpIdx2);
+  }
   case RISCV::PseudoCCMOVGPRNoX0:
   case RISCV::PseudoCCMOVGPR: {
     // CCMOV can be commuted by inverting the condition.

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -604,15 +604,15 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
   let Inst{31-25} = {simm, funct2};
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
 class QCIMVCC<bits<3> funct3, string opcodestr>
     : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
                (ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
                opcodestr, "$rd, $rs1, $rs2, $rs3"> {
   let Constraints = "$rd = $rd_wb";
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
 class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
     : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
                (ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),

llvm/test/CodeGen/RISCV/select-bare.ll

@@ -26,8 +26,8 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
 ; RV32IXQCI-LABEL: bare_select:
 ; RV32IXQCI:       # %bb.0:
 ; RV32IXQCI-NEXT:    andi a0, a0, 1
-; RV32IXQCI-NEXT:    qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT:    mv a0, a2
+; RV32IXQCI-NEXT:    qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT:    mv a0, a1
 ; RV32IXQCI-NEXT:    ret
   %1 = select i1 %a, i32 %b, i32 %c
   ret i32 %1
@@ -53,8 +53,8 @@ define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
 ; RV32IXQCI-LABEL: bare_select_float:
 ; RV32IXQCI:       # %bb.0:
 ; RV32IXQCI-NEXT:    andi a0, a0, 1
-; RV32IXQCI-NEXT:    qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT:    mv a0, a2
+; RV32IXQCI-NEXT:    qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT:    mv a0, a1
 ; RV32IXQCI-NEXT:    ret
   %1 = select i1 %a, float %b, float %c
   ret float %1

llvm/test/CodeGen/RISCV/select-cc.ll

@@ -87,40 +87,40 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
 ;
 ; RV32IXQCI-LABEL: foo:
 ; RV32IXQCI:       # %bb.0:
-; RV32IXQCI-NEXT:    lw a5, 0(a1)
 ; RV32IXQCI-NEXT:    lw a2, 0(a1)
 ; RV32IXQCI-NEXT:    lw a4, 0(a1)
 ; RV32IXQCI-NEXT:    lw t5, 0(a1)
 ; RV32IXQCI-NEXT:    lw t4, 0(a1)
+; RV32IXQCI-NEXT:    lw t3, 0(a1)
 ; RV32IXQCI-NEXT:    lw t2, 0(a1)
-; RV32IXQCI-NEXT:    lw t1, 0(a1)
 ; RV32IXQCI-NEXT:    lw t0, 0(a1)
 ; RV32IXQCI-NEXT:    lw a7, 0(a1)
 ; RV32IXQCI-NEXT:    lw a6, 0(a1)
-; RV32IXQCI-NEXT:    lw t3, 0(a1)
 ; RV32IXQCI-NEXT:    lw a3, 0(a1)
-; RV32IXQCI-NEXT:    bltz t3, .LBB0_2
+; RV32IXQCI-NEXT:    lw t1, 0(a1)
+; RV32IXQCI-NEXT:    lw a5, 0(a1)
+; RV32IXQCI-NEXT:    bltz t1, .LBB0_2
 ; RV32IXQCI-NEXT:  # %bb.1:
-; RV32IXQCI-NEXT:    li t6, 0
-; RV32IXQCI-NEXT:    qc.mveq a5, a0, a5, a0
-; RV32IXQCI-NEXT:    qc.mvne a2, a5, a2, a5
-; RV32IXQCI-NEXT:    qc.mvltu a4, a4, a2, a2
-; RV32IXQCI-NEXT:    qc.mvgeu t5, a4, t5, a4
-; RV32IXQCI-NEXT:    qc.mvltu t4, t5, t4, t5
-; RV32IXQCI-NEXT:    qc.mvgeu t2, t2, t4, t4
-; RV32IXQCI-NEXT:    qc.mvlt t1, t1, t2, t2
-; RV32IXQCI-NEXT:    qc.mvge t0, t1, t0, t1
-; RV32IXQCI-NEXT:    qc.mvlt a7, t0, a7, t0
-; RV32IXQCI-NEXT:    qc.mvge a6, a6, a7, a7
-; RV32IXQCI-NEXT:    mv a3, t3
-; RV32IXQCI-NEXT:    qc.mvge a3, t6, t3, a6
+; RV32IXQCI-NEXT:    li a5, 0
+; RV32IXQCI-NEXT:    qc.mveq a2, a0, a2, a0
+; RV32IXQCI-NEXT:    qc.mvne a4, a2, a4, a2
+; RV32IXQCI-NEXT:    qc.mvltu t5, t5, a4, a4
+; RV32IXQCI-NEXT:    qc.mvgeu t4, t5, t4, t5
+; RV32IXQCI-NEXT:    qc.mvltu t3, t4, t3, t4
+; RV32IXQCI-NEXT:    qc.mvgeu t2, t2, t3, t3
+; RV32IXQCI-NEXT:    qc.mvlt t0, t0, t2, t2
+; RV32IXQCI-NEXT:    qc.mvge a7, t0, a7, t0
+; RV32IXQCI-NEXT:    qc.mvlt a6, a7, a6, a7
+; RV32IXQCI-NEXT:    qc.mvge a3, a3, a6, a6
+; RV32IXQCI-NEXT:    qc.mvlt a3, a5, t1, t1
+; RV32IXQCI-NEXT:    mv a5, a3
 ; RV32IXQCI-NEXT:  .LBB0_2:
 ; RV32IXQCI-NEXT:    lw a2, 0(a1)
 ; RV32IXQCI-NEXT:    lw a0, 0(a1)
 ; RV32IXQCI-NEXT:    li a1, 1024
-; RV32IXQCI-NEXT:    qc.mvlt a2, a1, a2, a3
+; RV32IXQCI-NEXT:    qc.mvlt a2, a1, a2, a5
 ; RV32IXQCI-NEXT:    li a1, 2046
-; RV32IXQCI-NEXT:    qc.mvltu a0, a1, t3, a2
+; RV32IXQCI-NEXT:    qc.mvltu a0, a1, t1, a2
 ; RV32IXQCI-NEXT:    ret
 ;
 ; RV64I-LABEL: foo:
@@ -417,8 +417,8 @@ define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z)
 ; RV32IXQCI:       # %bb.0:
 ; RV32IXQCI-NEXT:    lui a3, 1048560
 ; RV32IXQCI-NEXT:    addi a3, a3, -1
-; RV32IXQCI-NEXT:    qc.mvlt a2, a3, a0, a1
-; RV32IXQCI-NEXT:    mv a0, a2
+; RV32IXQCI-NEXT:    qc.mvge a1, a3, a0, a2
+; RV32IXQCI-NEXT:    mv a0, a1
 ; RV32IXQCI-NEXT:    ret
 ;
 ; RV64I-LABEL: select_sge_int16min:
@@ -471,10 +471,10 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
 ; RV32IXQCI-NEXT:    srli a0, a1, 31
 ; RV32IXQCI-NEXT:    xori a0, a0, 1
 ; RV32IXQCI-NEXT:    qc.mveqi a0, a1, -1, a6
-; RV32IXQCI-NEXT:    qc.mvnei a4, a0, 0, a2
-; RV32IXQCI-NEXT:    qc.mvnei a5, a0, 0, a3
-; RV32IXQCI-NEXT:    mv a0, a4
-; RV32IXQCI-NEXT:    mv a1, a5
+; RV32IXQCI-NEXT:    qc.mveqi a2, a0, 0, a4
+; RV32IXQCI-NEXT:    qc.mveqi a3, a0, 0, a5
+; RV32IXQCI-NEXT:    mv a0, a2
+; RV32IXQCI-NEXT:    mv a1, a3
 ; RV32IXQCI-NEXT:    ret
 ;
 ; RV64I-LABEL: select_sge_int32min: