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[X86] canCreateUndefOrPoisonForTargetNode/isGuaranteedNotToBeUndefOrPoisonForTargetNode - add X86ISD::PSHUFB handling #160842

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Merged
merged 1 commit into from
Sep 26, 2025
+5 −13
Merged

[X86] canCreateUndefOrPoisonForTargetNode/isGuaranteedNotToBeUndefOrPoisonForTargetNode - add X86ISD::PSHUFB handling #160842

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2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -45185,6 +45185,7 @@ bool X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(
case X86ISD::WrapperRIP:
return true;
case X86ISD::BLENDI:
case X86ISD::PSHUFB:
case X86ISD::PSHUFD:
case X86ISD::UNPCKL:
case X86ISD::UNPCKH:
Expand Down Expand Up @@ -45251,6 +45252,7 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode(
case X86ISD::BLENDV:
return false;
// SSE target shuffles.
case X86ISD::PSHUFB:
case X86ISD::PSHUFD:
case X86ISD::UNPCKL:
case X86ISD::UNPCKH:
Expand Down
16 changes: 3 additions & 13 deletions llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
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Expand Up @@ -897,19 +897,9 @@ define i32 @mask_z1z3_v16i8(<16 x i8> %a0) {
}

define <16 x i8> @freeze_pshufb_v16i8(<16 x i8> %a0) {
; SSE-LABEL: freeze_pshufb_v16i8:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; SSE-NEXT: pshufb %xmm1, %xmm0
; SSE-NEXT: pshufb %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: freeze_pshufb_v16i8:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
; CHECK-LABEL: freeze_pshufb_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%s0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
%f0 = freeze <16 x i8> %s0
%s1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %f0, <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
Expand Down