[Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig

[ChunyuLiao]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Liao Chunyu (ChunyuLiao)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/161058.diff

1 Files Affected:

• (modified) llvm/docs/RISCVUsage.rst (+4-6)

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 7b1a6ce834919..d3c62c1b0d821 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -120,6 +120,8 @@ on support follow.
      ``H``             Assembly Support
      ``M``             Supported
      ``Q``             Assembly Support
+     ``Sdext``         Assembly Support
+     ``Sdtrig``        Assembly Support
      ``Sha``           Supported
      ``Shcounterenw``  Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Shgatpa``       Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
@@ -132,6 +134,7 @@ on support follow.
      ``Smcdeleg``      Supported
      ``Smcntrpmf``     Supported
      ``Smcsrind``      Supported
+     ``Smctr``         Assembly Support
      ``Smdbltrp``      Supported
      ``Smepmp``        Supported
      ``Smmpm``         Supported
@@ -144,6 +147,7 @@ on support follow.
      ``Sscofpmf``      Assembly Support
      ``Sscounterenw``  Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Sscsrind``      Supported
+     ``Ssctr``         Assembly Support
      ``Ssdbltrp``      Supported
      ``Ssnpm``         Supported
      ``Sspm``          Supported
@@ -337,12 +341,6 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-zvbc32e``, ``experimental-zvkgs``
   LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
 
-``experimental-sdext``, ``experimental-sdtrig``
-  LLVM implements the `1.0-rc4 specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf>`__.
-
-``experimental-smctr``, ``experimental-ssctr``
-  LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.
-
 ``experimental-svukte``
   LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.
 

[sunshaoce]

Can we also give these extensions a See note like Sscounterenw? I think this is very convenient.

[ChunyuLiao]

Can we also give these extensions a See note like Sscounterenw? I think this is very convenient.

They have assembly instructions, and are outside the scope of the riscv profile.
#120936
#105148

Do we need to add the spec document to RISCVUsage.rst?
https://github.com/riscv/riscv-debug-spec/releases
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3

[sunshaoce]

Do we need to add the spec document to RISCVUsage.rst? https://github.com/riscv/riscv-debug-spec/releases https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3

Yes, adding a .. _riscv-debug-spec-note: would be good. That way readers have a clear reference to the spec.

[ChunyuLiao]

Add Smctr, Ssctr,Sdext and Sdtrig spec docs. We can list the specs of other extensions, if needed.

[topperc]

Smctr and Ssctr have been integrated into the riscv-isa-manual I think.

[ChunyuLiao]

delete Smctr and Ssctr spec.

[sunshaoce]

LGTM