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[SPARC] Prevent meta instructions from being inserted into delay slots #161111

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Merged
merged 3 commits into from
Oct 3, 2025
Merged

[SPARC] Prevent meta instructions from being inserted into delay slots #161111

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ab7b98f
[SPARC] Prevent generic opcodes from being inserted into delay slots
koachan Sep 29, 2025
43a45db
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koachan Oct 3, 2025
1b209d8
Remove redundant debug check
koachan Oct 3, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/DelaySlotFiller.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -206,8 +206,8 @@ Filler::findDelayInstr(MachineBasicBlock &MBB,
if (!done)
--I;

// skip debug instruction
if (I->isDebugInstr())
// Skip meta instructions.
if (I->isMetaInstruction())
continue;

if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
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25 changes: 25 additions & 0 deletions llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
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Expand Up @@ -184,4 +184,29 @@ entry:
ret i32 %2
}

define i32 @test_generic_inst(i32 %arg) #0 {
;CHECK-LABEL: test_generic_inst:
;CHECK: ! fake_use: {{.*}}
;CHECK: bne {{.*}}
;CHECK-NEXT: nop
%bar1 = call i32 @bar(i32 %arg)
%even = and i32 %bar1, 1
%cmp = icmp eq i32 %even, 0
; This shouldn't get reordered into a delay slot
call void (...) @llvm.fake.use(i32 %arg)
br i1 %cmp, label %true, label %false
true:
%bar2 = call i32 @bar(i32 %bar1)
br label %cont

false:
%inc = add nsw i32 %bar1, 1
br label %cont

cont:
%ret = phi i32 [ %bar2, %true ], [ %inc, %false ]
ret i32 %ret
}

declare void @llvm.fake.use(...)
attributes #0 = { nounwind "disable-tail-calls"="true" }