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AMDGPU: Add peephole opt baseline tests #161309

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148 changes: 148 additions & 0 deletions llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -80,3 +80,151 @@ body: |
%4:vreg_128 = REG_SEQUENCE %3.sub0, %subreg.sub0, %3.sub1, %subreg.sub1, %3.sub2, %subreg.sub2, %3.sub3, %subreg.sub3
KILL implicit %4
...

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Perhaps add a comment that those tests document missed fold?

name: copy_vreg_64_subreg_from_vgpr_reg_sequence
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: copy_vreg_64_subreg_from_vgpr_reg_sequence
; GCN: liveins: $vgpr0, $vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN-NEXT: $vgpr0 = COPY [[COPY2]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%3:vgpr_32 = COPY %2.sub0
$vgpr0 = COPY %3
...

---
name: copy_vreg_64_subreg_from_vgpr_reg_sequence_extra_copy
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: copy_vreg_64_subreg_from_vgpr_reg_sequence_extra_copy
; GCN: liveins: $vgpr0, $vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: $vgpr0 = COPY [[COPY3]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%3:vreg_64 = COPY %2
%4:vgpr_32 = COPY %3.sub0
$vgpr0 = COPY %4
...

---
name: copy_av_64_subreg_from_vgpr_reg_sequence
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: copy_av_64_subreg_from_vgpr_reg_sequence
; GCN: liveins: $vgpr0, $vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[COPY2:%[0-9]+]]:av_64_align2 = COPY [[REG_SEQUENCE]]
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; GCN-NEXT: $vgpr0 = COPY [[COPY3]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%3:av_64_align2 = COPY %2
%4:vgpr_32 = COPY %3.sub0
$vgpr0 = COPY %4
...

---
name: copy_vreg_64_subreg_from_vgpr_reg_sequence_with_sub0_compose
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: copy_vreg_64_subreg_from_vgpr_reg_sequence_with_sub0_compose
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN-NEXT: $vgpr0 = COPY [[COPY2]]
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1
%3:vgpr_32 = COPY %2.sub0
$vgpr0 = COPY %3
...

---
name: copy_vreg_64_subreg_from_vgpr_reg_sequence_with_sub1_compose
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: copy_vreg_64_subreg_from_vgpr_reg_sequence_with_sub1_compose
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]].sub1, %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN-NEXT: $vgpr0 = COPY [[COPY2]]
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr1
%2:vreg_64 = REG_SEQUENCE %0.sub1, %subreg.sub0, %1, %subreg.sub1
%3:vgpr_32 = COPY %2.sub0
$vgpr0 = COPY %3
...

---
name: copy_vreg_64_subreg_from_multiple_vgpr_reg_sequence
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GCN-LABEL: name: copy_vreg_64_subreg_from_multiple_vgpr_reg_sequence
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
; GCN-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
; GCN-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE2]].sub1_sub2
; GCN-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
; GCN-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
; GCN-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[COPY4]]
; GCN-NEXT: $vgpr2_vgpr3 = COPY [[COPY5]]
; GCN-NEXT: $vgpr4_vgpr5 = COPY [[COPY6]]
; GCN-NEXT: $vgpr6 = COPY [[COPY7]]
; GCN-NEXT: $vgpr6 = COPY [[COPY8]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%2:vgpr_32 = COPY $vgpr2
%3:vgpr_32 = COPY $vgpr3
%4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%5:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
%6:vreg_128 = REG_SEQUENCE %4, %subreg.sub0_sub1, %5, %subreg.sub2_sub3
%7:vreg_64 = COPY %6.sub0_sub1
%8:vreg_64 = COPY %6.sub1_sub2
%9:vreg_64 = COPY %6.sub2_sub3
%10:vgpr_32 = COPY %6.sub2
%11:vgpr_32 = COPY %6.sub0
$vgpr0_vgpr1 = COPY %7
$vgpr2_vgpr3 = COPY %8
$vgpr4_vgpr5 = COPY %9
$vgpr6 = COPY %10
$vgpr6 = COPY %11
...