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[RISCV] Add commutative support for Qualcomm uC Xqcics extension #161328

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Merged
merged 6 commits into from
Oct 1, 2025
Merged

[RISCV] Add commutative support for Qualcomm uC Xqcics extension #161328

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ed905d6
[RISCV] Add commutative support for Xqcics
hchandel Sep 29, 2025
5f3308f
Precommit xqcics.ll with avoidable moves
hchandel Sep 29, 2025
15da9e7
fixup! Update tests
hchandel Sep 29, 2025
7ccb5b2
fixup! Remove CloneIfNew
hchandel Sep 30, 2025
c4f8b1f
Merge branch 'main' into Xqcics_comm
hchandel Oct 1, 2025
d28efbb
fixup! clang-format
hchandel Oct 1, 2025
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10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3793,6 +3793,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return false;
// Operands 1 and 2 are commutable, if we switch the opcode.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
case RISCV::QC_SELECTIEQ:
case RISCV::QC_SELECTINE:
case RISCV::QC_SELECTIIEQ:
case RISCV::QC_SELECTIINE:
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
case RISCV::QC_MVEQ:
case RISCV::QC_MVNE:
case RISCV::QC_MVLT:
Expand Down Expand Up @@ -4018,6 +4023,11 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
case RISCV::QC_SELECTIEQ:
case RISCV::QC_SELECTINE:
case RISCV::QC_SELECTIIEQ:
case RISCV::QC_SELECTIINE:
return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
case RISCV::QC_MVEQ:
case RISCV::QC_MVNE:
case RISCV::QC_MVLT:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
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Expand Up @@ -524,7 +524,7 @@ class QCIRVInstRI<bits<1> funct1, DAGOperand InTyImm11,
let Inst{30-20} = imm11;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCISELECTIICC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2),
Expand All @@ -537,7 +537,7 @@ class QCISELECTIICC<bits<3> funct3, string opcodestr>
let rs2 = simm1;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCISELECTICC<bits<3> funct3, string opcodestr>
: RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2),
Expand Down
124 changes: 124 additions & 0 deletions llvm/test/CodeGen/RISCV/xqcics.ll
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Expand Up @@ -690,3 +690,127 @@ entry:
ret i32 %sel
}

define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: beq a1, a0, .LBB21_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB21_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq1:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_eq1:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.line a2, a1, a0, 11
; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %a
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}

define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: bne a1, a0, .LBB22_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB22_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ne1:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_ne1:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.lieq a2, a1, a0, 11
; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %a
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}


define i32 @select_cc_example_eq2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: beq a1, a0, .LBB23_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB23_2:
; RV32I-NEXT: li a0, 15
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq2:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_eq2:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.selectiieq a0, a1, 15, 11
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %b, %a
%sel = select i1 %cmp, i32 15, i32 11
ret i32 %sel
}

define i32 @select_cc_example_ne2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: bne a1, a0, .LBB24_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: li a0, 15
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ne2:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCICS-NEXT: ret
;
; RV32IXQCICM-LABEL: select_cc_example_ne2:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: qc.selectiine a0, a1, 15, 11
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %b, %a
%sel = select i1 %cmp, i32 15, i32 11
ret i32 %sel
}