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AMDGPU: Use srcvalue and delete Ignore complex pattern #161359

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Merged
merged 1 commit into from
Sep 30, 2025
Merged

AMDGPU: Use srcvalue and delete Ignore complex pattern #161359

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4 changes: 0 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPUGISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,6 @@
include "AMDGPU.td"
include "AMDGPUCombine.td"

def gi_ignore :
GIComplexOperandMatcher<s32, "selectIgnore">,
GIComplexPatternEquiv<Ignore>;

def sd_vsrc0 : ComplexPattern<i32, 1, "">;
def gi_vsrc0 :
GIComplexOperandMatcher<s32, "selectVSRC0">,
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Expand Up @@ -4312,8 +4312,6 @@ bool AMDGPUDAGToDAGISel::SelectBITOP3(SDValue In, SDValue &Src0, SDValue &Src1,
return true;
}

bool AMDGPUDAGToDAGISel::SelectIgnore(SDValue In) const { return true; }

SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
if (In.isUndef())
return CurDAG->getUNDEF(MVT::i32);
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
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Expand Up @@ -305,8 +305,6 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
void SelectWAVE_ADDRESS(SDNode *N);
void SelectSTACKRESTORE(SDNode *N);

bool SelectIgnore(SDValue In) const;

protected:
// Include the pieces autogenerated from the target description.
#include "AMDGPUGenDAGISel.inc"
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8 changes: 0 additions & 8 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -4266,14 +4266,6 @@ Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
return Src;
}

InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectIgnore(MachineOperand &Root) const {
// Don't render anything.
ComplexRendererFns Renderers;
Renderers.emplace();
return Renderers;
}

///
/// This will select either an SGPR or VGPR operand and will save us from
/// having to write an extra tablegen pattern.
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3 changes: 0 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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Expand Up @@ -166,9 +166,6 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
MachineOperand Root, MachineInstr *InsertPt,
bool ForceVGPR = false) const;

InstructionSelector::ComplexRendererFns
selectIgnore(MachineOperand &Root) const;

InstructionSelector::ComplexRendererFns
selectVCSRC(MachineOperand &Root) const;

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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -1710,8 +1710,6 @@ def VOP3PMadMixBF16Mods : ComplexPattern<untyped, 2, "SelectVOP3PMadMixBF16Mods"
def VINTERPMods : ComplexPattern<untyped, 2, "SelectVINTERPMods">;
def VINTERPModsHi : ComplexPattern<untyped, 2, "SelectVINTERPModsHi">;

def Ignore : ComplexPattern<untyped, 0, "SelectIgnore">;

//===----------------------------------------------------------------------===//
// SI assembler operands
//===----------------------------------------------------------------------===//
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SOPInstructions.td
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Expand Up @@ -1617,7 +1617,7 @@ def S_BARRIER_WAIT : SOPP_Pseudo <"s_barrier_wait", (ins i16imm:$simm16), "$simm
}

def S_BARRIER_LEAVE : SOPP_Pseudo <"s_barrier_leave",
(ins), "", [(int_amdgcn_s_barrier_leave (Ignore))] > {
(ins), "", [(int_amdgcn_s_barrier_leave (i16 srcvalue))] > {
let SchedRW = [WriteBarrier];
let simm16 = 0;
let fixed_imm = 1;
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