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[RISCV] Use LBU for anyext i8 atomic_load. #161588

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Merged
merged 1 commit into from
Oct 2, 2025
+27 −25
Merged

[RISCV] Use LBU for anyext i8 atomic_load. #161588

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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -109,8 +109,9 @@ def : LdPat<extloadi8, LBU, i16>; // Prefer unsigned due to no c.lb in Zcb.
def : StPat<truncstorei8, SB, GPR, i16>;

let Predicates = [HasAtomicLdSt] in {
def : LdPat<atomic_load_aext_8, LB, i16>;
def : LdPat<atomic_load_nonext_16, LH, i16>;
// Prefer unsigned due to no c.lb in Zcb.
def : LdPat<atomic_load_aext_8, LBU, i16>;
def : LdPat<atomic_load_nonext_16, LH, i16>;

def : StPat<atomic_store_8, SB, GPR, i16>;
def : StPat<atomic_store_16, SH, GPR, i16>;
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7 changes: 4 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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Expand Up @@ -165,10 +165,11 @@ class seq_cst_store<PatFrag base>
// any ordering. This is necessary because AtomicExpandPass has added fences to
// atomic load/stores and changed them to unordered ones.
let Predicates = [HasAtomicLdSt] in {
def : LdPat<relaxed_load<atomic_load_asext_8>, LB>;
// Use unsigned for aext due to no c.lb in Zcb.
def : LdPat<relaxed_load<atomic_load_sext_8>, LB>;
def : LdPat<relaxed_load<atomic_load_azext_8>, LBU>;
def : LdPat<relaxed_load<atomic_load_asext_16>, LH>;
def : LdPat<relaxed_load<atomic_load_zext_8>, LBU>;
def : LdPat<relaxed_load<atomic_load_zext_16>, LHU>;
def : LdPat<relaxed_load<atomic_load_zext_16>, LHU>;

def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
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40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll
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Expand Up @@ -37,7 +37,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
;
; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: lbu a0, 0(a0)
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomic_load_i8_unordered:
Expand All @@ -52,7 +52,7 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
;
; RV64IA-LABEL: atomic_load_i8_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: lbu a0, 0(a0)
; RV64IA-NEXT: ret
%1 = load atomic i8, ptr %a unordered, align 1
ret i8 %1
Expand All @@ -71,7 +71,7 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
;
; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
; RV32IA-NEXT: lbu a0, 0(a0)
; RV32IA-NEXT: ret
;
; RV64I-LABEL: atomic_load_i8_monotonic:
Expand All @@ -86,7 +86,7 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
;
; RV64IA-LABEL: atomic_load_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
; RV64IA-NEXT: lbu a0, 0(a0)
; RV64IA-NEXT: ret
%1 = load atomic i8, ptr %a monotonic, align 1
ret i8 %1
Expand All @@ -105,13 +105,13 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
;
; RV32IA-WMO-LABEL: atomic_load_i8_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lb a0, 0(a0)
; RV32IA-WMO-NEXT: lbu a0, 0(a0)
; RV32IA-WMO-NEXT: fence r, rw
; RV32IA-WMO-NEXT: ret
;
; RV32IA-TSO-LABEL: atomic_load_i8_acquire:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: lb a0, 0(a0)
; RV32IA-TSO-NEXT: lbu a0, 0(a0)
; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomic_load_i8_acquire:
Expand All @@ -126,35 +126,35 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
;
; RV64IA-WMO-LABEL: atomic_load_i8_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lb a0, 0(a0)
; RV64IA-WMO-NEXT: lbu a0, 0(a0)
; RV64IA-WMO-NEXT: fence r, rw
; RV64IA-WMO-NEXT: ret
;
; RV64IA-TSO-LABEL: atomic_load_i8_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: lb a0, 0(a0)
; RV64IA-TSO-NEXT: lbu a0, 0(a0)
; RV64IA-TSO-NEXT: ret
;
; RV32IA-WMO-TRAILING-FENCE-LABEL: atomic_load_i8_acquire:
; RV32IA-WMO-TRAILING-FENCE: # %bb.0:
; RV32IA-WMO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV32IA-WMO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV32IA-WMO-TRAILING-FENCE-NEXT: fence r, rw
; RV32IA-WMO-TRAILING-FENCE-NEXT: ret
;
; RV32IA-TSO-TRAILING-FENCE-LABEL: atomic_load_i8_acquire:
; RV32IA-TSO-TRAILING-FENCE: # %bb.0:
; RV32IA-TSO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV32IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV32IA-TSO-TRAILING-FENCE-NEXT: ret
;
; RV64IA-WMO-TRAILING-FENCE-LABEL: atomic_load_i8_acquire:
; RV64IA-WMO-TRAILING-FENCE: # %bb.0:
; RV64IA-WMO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV64IA-WMO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV64IA-WMO-TRAILING-FENCE-NEXT: fence r, rw
; RV64IA-WMO-TRAILING-FENCE-NEXT: ret
;
; RV64IA-TSO-TRAILING-FENCE-LABEL: atomic_load_i8_acquire:
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
; RV64IA-TSO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV64IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
%1 = load atomic i8, ptr %a acquire, align 1
ret i8 %1
Expand All @@ -174,14 +174,14 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV32IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
; RV32IA-WMO-NEXT: lb a0, 0(a0)
; RV32IA-WMO-NEXT: lbu a0, 0(a0)
; RV32IA-WMO-NEXT: fence r, rw
; RV32IA-WMO-NEXT: ret
;
; RV32IA-TSO-LABEL: atomic_load_i8_seq_cst:
; RV32IA-TSO: # %bb.0:
; RV32IA-TSO-NEXT: fence rw, rw
; RV32IA-TSO-NEXT: lb a0, 0(a0)
; RV32IA-TSO-NEXT: lbu a0, 0(a0)
; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomic_load_i8_seq_cst:
Expand All @@ -197,40 +197,40 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV64IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
; RV64IA-WMO-NEXT: lb a0, 0(a0)
; RV64IA-WMO-NEXT: lbu a0, 0(a0)
; RV64IA-WMO-NEXT: fence r, rw
; RV64IA-WMO-NEXT: ret
;
; RV64IA-TSO-LABEL: atomic_load_i8_seq_cst:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: fence rw, rw
; RV64IA-TSO-NEXT: lb a0, 0(a0)
; RV64IA-TSO-NEXT: lbu a0, 0(a0)
; RV64IA-TSO-NEXT: ret
;
; RV32IA-WMO-TRAILING-FENCE-LABEL: atomic_load_i8_seq_cst:
; RV32IA-WMO-TRAILING-FENCE: # %bb.0:
; RV32IA-WMO-TRAILING-FENCE-NEXT: fence rw, rw
; RV32IA-WMO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV32IA-WMO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV32IA-WMO-TRAILING-FENCE-NEXT: fence r, rw
; RV32IA-WMO-TRAILING-FENCE-NEXT: ret
;
; RV32IA-TSO-TRAILING-FENCE-LABEL: atomic_load_i8_seq_cst:
; RV32IA-TSO-TRAILING-FENCE: # %bb.0:
; RV32IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
; RV32IA-TSO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV32IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV32IA-TSO-TRAILING-FENCE-NEXT: ret
;
; RV64IA-WMO-TRAILING-FENCE-LABEL: atomic_load_i8_seq_cst:
; RV64IA-WMO-TRAILING-FENCE: # %bb.0:
; RV64IA-WMO-TRAILING-FENCE-NEXT: fence rw, rw
; RV64IA-WMO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV64IA-WMO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV64IA-WMO-TRAILING-FENCE-NEXT: fence r, rw
; RV64IA-WMO-TRAILING-FENCE-NEXT: ret
;
; RV64IA-TSO-TRAILING-FENCE-LABEL: atomic_load_i8_seq_cst:
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
; RV64IA-TSO-TRAILING-FENCE-NEXT: lb a0, 0(a0)
; RV64IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
%1 = load atomic i8, ptr %a seq_cst, align 1
ret i8 %1
Expand Down