[X86] combineBitcastvxi1 - bail out on soft-float targets

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -45457,7 +45457,8 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
                                   const SDLoc &DL,
                                   const X86Subtarget &Subtarget) {
   EVT SrcVT = Src.getValueType();
-  if (!SrcVT.isSimple() || SrcVT.getScalarType() != MVT::i1)
+  if (Subtarget.useSoftFloat() || !SrcVT.isSimple() ||
+      SrcVT.getScalarType() != MVT::i1)
     return SDValue();
 
   // Recognize the IR pattern for the movmsk intrinsic under SSE1 before type

llvm/test/CodeGen/X86/pr161693.ll

@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define void @PR161693() #0 {
+; CHECK-LABEL: PR161693:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    movzbl (%rax), %eax
+; CHECK-NEXT:    andb $-33, %al
+; CHECK-NEXT:    addb $-71, %al
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_1: # %loop
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    cmpb $-6, %al
+; CHECK-NEXT:    setb %cl
+; CHECK-NEXT:    leal (%rcx,%rcx), %edx
+; CHECK-NEXT:    orb %cl, %dl
+; CHECK-NEXT:    leal (,%rdx,4), %ecx
+; CHECK-NEXT:    orb %dl, %cl
+; CHECK-NEXT:    je .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %exit
+; CHECK-NEXT:    retq
+start:
+  br label %loop
+
+loop:
+  %.val.i.i89 = load <16 x i8>, ptr poison, align 1
+  %.not49.i = icmp ult <16 x i8> zeroinitializer, splat (i8 -10)
+  %i = and <16 x i8> %.val.i.i89, splat (i8 -33)
+  %i1 = add <16 x i8> %i, splat (i8 -71)
+  %.not51.i = icmp ult <16 x i8> %i1, splat (i8 -6)
+  %.not46.i = and <16 x i1> %.not49.i, %.not51.i
+  %i2 = bitcast <16 x i1> %.not46.i to i16
+  %_0.i = icmp eq i16 %i2, 0
+  br i1 %_0.i, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+attributes #0 = { "target-features"="+soft-float" }