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[RISCV][GISel] Share an atomic load isel pattern GISel RV64 and SDAG RV32. NFC #161721

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Merged
merged 1 commit into from
Oct 2, 2025
Merged

[RISCV][GISel] Share an atomic load isel pattern GISel RV64 and SDAG RV32. NFC #161721

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVGISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ let Predicates = [HasAtomicLdSt] in {
}

let Predicates = [HasAtomicLdSt, IsRV64] in {
def : LdPat<atomic_load_nonext_32, LW, i32>;
// Load pattern is in RISCVInstrInfoA.td and shared with RV32.
def : StPat<atomic_store_32, SW, GPR, i32>;
}

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9 changes: 4 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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Expand Up @@ -174,15 +174,14 @@ let Predicates = [HasAtomicLdSt] in {
def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
}

let Predicates = [HasAtomicLdSt, IsRV32] in {
def : LdPat<relaxed_load<atomic_load_nonext_32>, LW>;
// Used by GISel for RV32 and RV64.
def : LdPat<relaxed_load<atomic_load_nonext_32>, LW, i32>;
}

let Predicates = [HasAtomicLdSt, IsRV64] in {
def : LdPat<relaxed_load<atomic_load_asext_32>, LW>;
def : LdPat<relaxed_load<atomic_load_zext_32>, LWU>;
def : LdPat<relaxed_load<atomic_load_asext_32>, LW, i64>;
def : LdPat<relaxed_load<atomic_load_zext_32>, LWU, i64>;
def : LdPat<relaxed_load<atomic_load_nonext_64>, LD, i64>;
def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
}
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