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[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass #161764

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Merged
merged 1 commit into from
Oct 3, 2025
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[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass #161764

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4 changes: 3 additions & 1 deletion llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Expand Up @@ -931,7 +931,9 @@ static MachineOperand *lookUpCopyChain(const SIInstrInfo &TII,
for (MachineInstr *SubDef = MRI.getVRegDef(SrcReg);
SubDef && TII.isFoldableCopy(*SubDef);
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I haven't checked the whole call chain if this property is already checked, but we should probably check that src_modifiers are 0 on the v_mov_b16 inside isFoldableCopy. I don't think we will set them, but safer to check. That can be a separate PR.

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Right. I think this FoldableCopy need to updated as well. I'll create another patch for the clean up, might also replace the if else check with the helper

SubDef = MRI.getVRegDef(Sub->getReg())) {
MachineOperand &SrcOp = SubDef->getOperand(1);
unsigned SrcIdx = TII.getFoldableCopySrcIdx(*SubDef);
MachineOperand &SrcOp = SubDef->getOperand(SrcIdx);

if (SrcOp.isImm())
return &SrcOp;
if (!SrcOp.isReg() || SrcOp.getReg().isPhysical())
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26 changes: 26 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -3435,6 +3435,32 @@ bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
}
}

unsigned SIInstrInfo::getFoldableCopySrcIdx(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::V_MOV_B16_t16_e32:
case AMDGPU::V_MOV_B16_t16_e64:
return 2;
case AMDGPU::V_MOV_B32_e32:
case AMDGPU::V_MOV_B32_e64:
case AMDGPU::V_MOV_B64_PSEUDO:
case AMDGPU::V_MOV_B64_e32:
case AMDGPU::V_MOV_B64_e64:
case AMDGPU::S_MOV_B32:
case AMDGPU::S_MOV_B64:
case AMDGPU::S_MOV_B64_IMM_PSEUDO:
case AMDGPU::COPY:
case AMDGPU::WWM_COPY:
case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
case AMDGPU::V_ACCVGPR_READ_B32_e64:
case AMDGPU::V_ACCVGPR_MOV_B32:
case AMDGPU::AV_MOV_B32_IMM_PSEUDO:
case AMDGPU::AV_MOV_B64_IMM_PSEUDO:
return 1;
default:
llvm_unreachable("MI is not a foldable copy");
}
}

static constexpr AMDGPU::OpName ModifierOpNames[] = {
AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -417,6 +417,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
const MachineInstr &MIb) const override;

static bool isFoldableCopy(const MachineInstr &MI);
static unsigned getFoldableCopySrcIdx(const MachineInstr &MI);

void removeModOperands(MachineInstr &MI) const;

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25 changes: 25 additions & 0 deletions llvm/test/CodeGen/AMDGPU/true16-fold.mir
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Expand Up @@ -57,6 +57,7 @@ body: |
%4:vgpr_16 = COPY %3:sgpr_lo16
%5:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, %0:sreg_32, 0, killed %1:sreg_32, 0, killed %4:vgpr_16, 0, 0, implicit $exec
S_ENDPGM 0, implicit %5
...

---
name: fold_16bit_madmix_clamp
Expand Down Expand Up @@ -207,3 +208,27 @@ body: |
$vgpr0 = COPY %4
S_ENDPGM 0, implicit $vgpr0
...

---
name: fold_imm16_across_reg_sequence
tracksRegLiveness: true
registers:
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: fold_imm16_across_reg_sequence
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B16_t16_e64_1:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_MOV_B16_t16_e64_]], %subreg.lo16, [[V_MOV_B16_t16_e64_1]], %subreg.hi16
; CHECK-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, -1, 0, -1, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F32_e64_]]
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
%0:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
%1:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
%2:vgpr_32 = REG_SEQUENCE %0, %subreg.lo16, %1, %subreg.hi16
%3:vgpr_32 = nofpexcept V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
$vgpr0 = COPY %3
S_ENDPGM 0, implicit $vgpr0
...
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