AMDGPU: Stop trying to constrain register class of post-RA-pseudos

[arsenm]

This is trying to constrain the register class of a physical register,
which makes no sense.

[arsenm]

• CodeGen: Stop checking for physregs in constrainRegClass #161795
• AMDGPU: Fix constrain register logic for physregs #161794
• AMDGPU: Fix trying to constrain physical registers in spill handling #161793
• AMDGPU: Stop trying to constrain register class of post-RA-pseudos #161792 👈 (View in Graphite)
• AMDGPU: Remove dead code trying to constrain a physical register #161790
• main

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

This is trying to constrain the register class of a physical register,
which makes no sense.

---

Full diff: https://github.com/llvm/llvm-project/pull/161792.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (-2)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index fe6b8b96cbd57..cda8069936af2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2112,8 +2112,6 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
 
   case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
     MI.setDesc(get(AMDGPU::V_READLANE_B32));
-    MI.getMF()->getRegInfo().constrainRegClass(MI.getOperand(0).getReg(),
-                                               &AMDGPU::SReg_32_XM0RegClass);
     break;
   case AMDGPU::AV_MOV_B32_IMM_PSEUDO: {
     Register Dst = MI.getOperand(0).getReg();