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AMDGPU: Fix trying to constrain physical registers in spill handling #161793

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Merged
merged 3 commits into from
Oct 3, 2025
Merged

AMDGPU: Fix trying to constrain physical registers in spill handling #161793

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633c244
AMDGPU: Remove dead code trying to constrain a physical register
arsenm Oct 3, 2025
cf04ae0
AMDGPU: Stop trying to constrain register class of post-RA-pseudos
arsenm Oct 3, 2025
fda29b4
AMDGPU: Fix trying to constrain physical registers in spill handling
arsenm Oct 3, 2025
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,8 @@ class PrologEpilogSGPRSpillBuilder {

buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL,
TmpVGPR, FI, FrameReg, DwordOff);
MRI.constrainRegClass(SubReg, &AMDGPU::SReg_32_XM0RegClass);
assert(SubReg.isPhysical());

BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
.addReg(TmpVGPR, RegState::Kill);
DwordOff += 4;
Expand Down
25 changes: 8 additions & 17 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -2112,8 +2112,6 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {

case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
MI.setDesc(get(AMDGPU::V_READLANE_B32));
MI.getMF()->getRegInfo().constrainRegClass(MI.getOperand(0).getReg(),
&AMDGPU::SReg_32_XM0RegClass);
break;
case AMDGPU::AV_MOV_B32_IMM_PSEUDO: {
Register Dst = MI.getOperand(0).getReg();
Expand Down Expand Up @@ -8117,21 +8115,14 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
// hope for the best.
if (Inst.isCopy() && DstReg.isPhysical() &&
RI.isVGPR(MRI, Inst.getOperand(1).getReg())) {
// TODO: Only works for 32 bit registers.
if (MRI.constrainRegClass(DstReg, &AMDGPU::SReg_32_XM0RegClass)) {
BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(),
get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
.add(Inst.getOperand(1));
} else {
Register NewDst =
MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(),
get(AMDGPU::V_READFIRSTLANE_B32), NewDst)
.add(Inst.getOperand(1));
BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY),
DstReg)
.addReg(NewDst);
}
Register NewDst = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(),
get(AMDGPU::V_READFIRSTLANE_B32), NewDst)
.add(Inst.getOperand(1));
BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY),
DstReg)
.addReg(NewDst);

Inst.eraseFromParent();
return;
}
Expand Down
10 changes: 3 additions & 7 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -2222,8 +2222,6 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI,
// Don't need to write VGPR out.
}

MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();

// Restore clobbered registers in the specified restore block.
MI = RestoreMBB.end();
SB.setMI(&RestoreMBB, MI);
Expand All @@ -2238,7 +2236,8 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI,
SB.NumSubRegs == 1
? SB.SuperReg
: Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
MRI.constrainRegClass(SubReg, &AMDGPU::SReg_32_XM0RegClass);

assert(SubReg.isPhysical());
bool LastSubReg = (i + 1 == e);
auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32),
SubReg)
Expand Down Expand Up @@ -3059,8 +3058,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (IsSALU && LiveSCC) {
Register NewDest;
if (IsCopy) {
MF->getRegInfo().constrainRegClass(ResultReg,
&AMDGPU::SReg_32_XM0RegClass);
assert(ResultReg.isPhysical());
NewDest = ResultReg;
} else {
NewDest = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
Expand Down Expand Up @@ -3190,8 +3188,6 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,

Register NewDest;
if (IsCopy) {
MF->getRegInfo().constrainRegClass(ResultReg,
&AMDGPU::SReg_32_XM0RegClass);
NewDest = ResultReg;
} else {
NewDest = RS->scavengeRegisterBackwards(
Expand Down
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