Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -823,6 +823,7 @@ static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) {
break;
case RISCV::fixup_riscv_rvc_jump:
case RISCV::fixup_riscv_rvc_branch:
case RISCV::fixup_riscv_rvc_imm:
case RISCV::fixup_riscv_jal:
return false;
}
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -688,6 +688,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
// the `jal` again in the assembler.
} else if (MIFrm == RISCVII::InstFormatCI) {
FixupKind = RISCV::fixup_riscv_rvc_imm;
AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcili);
} else if (MIFrm == RISCVII::InstFormatI) {
FixupKind = RISCV::fixup_riscv_12_i;
} else if (MIFrm == RISCVII::InstFormatQC_EB) {
Expand Down
37 changes: 37 additions & 0 deletions llvm/test/MC/RISCV/xqcili-linker-relaxation.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+experimental-xqcili \
# RUN: %s -filetype=obj -o - -riscv-add-build-attributes \
# RUN: | llvm-objdump -dr -M no-aliases - \
# RUN: | FileCheck %s

## This tests that we correctly emit relocations for linker relaxation when
## emitting `QC.E.LI` and `QC.LI`.

.section .text.ex1, "ax", @progbits
# CHECK-LABEL: <.text.ex1>:
blez a1, .L1
# CHECK-NEXT: bge zero, a1, 0x0 <.text.ex1>
# CHECK-NEXT: R_RISCV_BRANCH .L1{{$}}
qc.e.li a0, sym
# CHECK-NEXT: qc.e.li a0, 0x0
# CHECK-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
# CHECK-NEXT: R_RISCV_CUSTOM194 sym{{$}}
# CHECK-NEXT: R_RISCV_RELAX *ABS*{{$}}
.L1:
# CHECK: <.L1>:
ret
# CHECK-NEXT: c.jr ra

.section .text.ex2, "ax", @progbits
# CHECK-LABEL: <.text.ex2>:
blez a1, .L2
# CHECK-NEXT: bge zero, a1, 0x0 <.text.ex2>
# CHECK-NEXT: R_RISCV_BRANCH .L2{{$}}
qc.li a0, %qc.abs20(sym)
# CHECK-NEXT: qc.li a0, 0x0
# CHECK-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
# CHECK-NEXT: R_RISCV_CUSTOM192 sym{{$}}
# CHECK-NEXT: R_RISCV_RELAX *ABS*{{$}}
.L2:
# CHECK: <.L2>:
ret
# CHECK-NEXT: c.jr ra