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Oct 8, 2025
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[AArch64][llvm] Reject assembler for invalid TLBIP instructions #162090

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754e4ba
[AArch64][llvm] Reject assembler for invalid TLBIP instructions
jthackray Oct 6, 2025
20a482b
fixup! [AArch64][llvm] Reject assembler for invalid TLBIP instructions
jthackray Oct 7, 2025
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223 changes: 121 additions & 102 deletions llvm/lib/Target/AArch64/AArch64SystemOperands.td
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Original file line number Diff line number Diff line change
Expand Up @@ -816,8 +816,8 @@ def : BTI<"jc", 0b110>;
// TLBI (translation lookaside buffer invalidate) instruction options.
//===----------------------------------------------------------------------===//

class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2, bit needsreg> {
class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2, bit needsreg> {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
Expand All @@ -830,131 +830,150 @@ class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
}

def TLBITable : GenericTable {
let FilterClass = "TLBIEntry";
let CppTypeName = "TLBI";
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];

let PrimaryKey = ["Encoding"];
let PrimaryKeyName = "lookupTLBIByEncoding";
class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2, bit needsreg>
: TLBICommon<name, op1, crn, crm, op2, needsreg>;

class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2, bit needsreg>
: TLBICommon<name, op1, crn, crm, op2, needsreg>;

multiclass TLBITableBase {
def NAME # Table : GenericTable {
let FilterClass = NAME # "Entry";
let CppTypeName = NAME;
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
let PrimaryKey = ["Encoding"];
let PrimaryKeyName = "lookup" # NAME # "ByEncoding";
}
def lookup # NAME # ByName : SearchIndex {
let Table = !cast<GenericTable>(NAME # "Table");
let Key = ["Name"];
}
}

def lookupTLBIByName : SearchIndex {
let Table = TLBITable;
let Key = ["Name"];
}
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;

multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
bits<3> op2, bit needsreg = 1> {
def : TLBIEntry<name, op1, crn, crm, op2, needsreg>;
def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
if !eq(hasTLBIP, true) then {
def : TLBIPEntry<name, op1, crn, crm, op2, needsreg>;
def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
}
}

defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>;
defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>;
defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>;
defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>;
defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>;
defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>;
defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>;
defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
// hasTLBIP op1 CRn CRm op2 needsreg
defm : TLBI<"IPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b001>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b101>;
defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, 0>;
defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001>;
defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001>;
defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001>;
defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010>;
defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011>;
defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, 0>;
defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101>;
defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, 0>;
defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111>;
defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001>;
defm : TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101>;
defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, 0>;
defm : TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001>;
defm : TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001>;
defm : TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001>;
defm : TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010>;
defm : TLBI<"VAAE1", 1, 0b000, 0b1000, 0b0111, 0b011>;
defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, 0>;
defm : TLBI<"VALE1", 1, 0b000, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VALE2", 1, 0b100, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VALE3", 1, 0b110, 0b1000, 0b0111, 0b101>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, 0>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111>;

// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
let Requires = ["AArch64::FeatureTLB_RMI"] in {
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
// op1 CRn CRm op2
defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>;
defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>;
defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>;
defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>;
defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>;
// hasTLBIP op1 CRn CRm op2 needsreg
defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, 0>;
defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001>;
defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010>;
defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011>;
defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101>;
defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111>;
defm : TLBI<"IPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b000>;
defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100>;
defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001>;
defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101>;
defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, 0>;
defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001>;
defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101>;
defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, 0>;
defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, 0>;
defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, 0>;

// Armv8.4-A TLB Range Maintenance instructions:
// op1 CRn CRm op2
defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;
defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;
defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>;
defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
// hasTLBIP op1 CRn CRm op2 needsreg
defm : TLBI<"RVAE1", 1, 0b000, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011>;
defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111>;
defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011>;
defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAALE1IS", 1, 0b000, 0b1000, 0b0010, 0b111>;
defm : TLBI<"RVAE1OS", 1, 0b000, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVAAE1OS", 1, 0b000, 0b1000, 0b0101, 0b011>;
defm : TLBI<"RVALE1OS", 1, 0b000, 0b1000, 0b0101, 0b101>;
defm : TLBI<"RVAALE1OS", 1, 0b000, 0b1000, 0b0101, 0b111>;
defm : TLBI<"RIPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b010>;
defm : TLBI<"RIPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b110>;
defm : TLBI<"RIPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b010>;
defm : TLBI<"RIPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b110>;
defm : TLBI<"RIPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b011>;
defm : TLBI<"RIPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b111>;
defm : TLBI<"RVAE2", 1, 0b100, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVALE2", 1, 0b100, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAE2IS", 1, 0b100, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVALE2IS", 1, 0b100, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAE2OS", 1, 0b100, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVALE2OS", 1, 0b100, 0b1000, 0b0101, 0b101>;
defm : TLBI<"RVAE3", 1, 0b110, 0b1000, 0b0110, 0b001>;
defm : TLBI<"RVALE3", 1, 0b110, 0b1000, 0b0110, 0b101>;
defm : TLBI<"RVAE3IS", 1, 0b110, 0b1000, 0b0010, 0b001>;
defm : TLBI<"RVALE3IS", 1, 0b110, 0b1000, 0b0010, 0b101>;
defm : TLBI<"RVAE3OS", 1, 0b110, 0b1000, 0b0101, 0b001>;
defm : TLBI<"RVALE3OS", 1, 0b110, 0b1000, 0b0101, 0b101>;
} //FeatureTLB_RMI

// Armv9-A Realm Management Extension TLBI Instructions
let Requires = ["AArch64::FeatureRME"] in {
defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>;
defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>;
defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>;
defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>;
defm : TLBI<"RPAOS", 0, 0b110, 0b1000, 0b0100, 0b011>;
defm : TLBI<"RPALOS", 0, 0b110, 0b1000, 0b0100, 0b111>;
defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, 0>;
defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, 0>;
}

// Armv9.5-A TLBI VMALL for Dirty State
let Requires = ["AArch64::FeatureTLBIW"] in {
// op1, CRn, CRm, op2, needsreg
defm : TLBI<"VMALLWS2E1", 0b100, 0b1000, 0b0110, 0b010, 0>;
defm : TLBI<"VMALLWS2E1IS", 0b100, 0b1000, 0b0010, 0b010, 0>;
defm : TLBI<"VMALLWS2E1OS", 0b100, 0b1000, 0b0101, 0b010, 0>;
// op1, CRn, CRm, op2, needsreg
defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, 0>;
defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, 0>;
defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0>;
}

//===----------------------------------------------------------------------===//
Expand Down
22 changes: 11 additions & 11 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4020,23 +4020,23 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
if (HasnXSQualifier) {
Op = Op.drop_back(3);
}
const AArch64TLBI::TLBI *TLBIorig = AArch64TLBI::lookupTLBIByName(Op);
if (!TLBIorig)
const AArch64TLBIP::TLBIP *TLBIPorig = AArch64TLBIP::lookupTLBIPByName(Op);
if (!TLBIPorig)
return TokError("invalid operand for TLBIP instruction");
const AArch64TLBI::TLBI TLBI(
TLBIorig->Name, TLBIorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
TLBIorig->NeedsReg,
const AArch64TLBIP::TLBIP TLBIP(
TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
TLBIPorig->NeedsReg,
HasnXSQualifier
? TLBIorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
: TLBIorig->FeaturesRequired);
if (!TLBI.haveFeatures(getSTI().getFeatureBits())) {
? TLBIPorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
: TLBIPorig->FeaturesRequired);
if (!TLBIP.haveFeatures(getSTI().getFeatureBits())) {
std::string Name =
std::string(TLBI.Name) + (HasnXSQualifier ? "nXS" : "");
std::string(TLBIP.Name) + (HasnXSQualifier ? "nXS" : "");
std::string Str("TLBIP " + Name + " requires: ");
setRequiredFeatureString(TLBI.getRequiredFeatures(), Str);
setRequiredFeatureString(TLBIP.getRequiredFeatures(), Str);
return TokError(Str);
}
createSysAlias(TLBI.Encoding, Operands, S);
createSysAlias(TLBIP.Encoding, Operands, S);
}

Lex(); // Eat operand.
Expand Down
7 changes: 4 additions & 3 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1066,12 +1066,13 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
Encoding &= ~(1 << 7);
}

const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
const AArch64TLBIP::TLBIP *TLBIP =
AArch64TLBIP::lookupTLBIPByEncoding(Encoding);
if (!TLBIP || !TLBIP->haveFeatures(STI.getFeatureBits()))
return false;

Ins = "tlbip\t";
Name = std::string(TLBI->Name);
Name = std::string(TLBIP->Name);
if (CnVal == 9)
Name += "nXS";
} else
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,13 @@ namespace llvm {
}
}

namespace llvm {
namespace AArch64TLBIP {
#define GET_TLBIPTable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP
} // namespace llvm

namespace llvm {
namespace AArch64SVCR {
#define GET_SVCRsList_IMPL
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
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Expand Up @@ -795,6 +795,14 @@ namespace AArch64TLBI {
#include "AArch64GenSystemOperands.inc"
}

namespace AArch64TLBIP {
struct TLBIP : SysAliasReg {
using SysAliasReg::SysAliasReg;
};
#define GET_TLBIPTable_DECL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP

namespace AArch64II {
/// Target Operand Flag enum.
enum TOF {
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