[GlobalIsel] Add failure memory order to LegalityQuery (NFC) #162284
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The `cmpxchg` instruction has two memory orders, one for success and one for failure. Prior to this patch LegalityQuery only exposed a single memory order, that of the success case. This meant that it was not generally possible to legalize `cmpxchg` instructions based on their memory orders. Add a `FailureOrdering` field to `LegalityQuery::MemDesc`, it is only set for `cmpxchg` instructions, otherwise it is `NotAtomic`. I didn't rename `Ordering` to `SuccessOrdering` or similar to avoid breaking changes for out of tree targets. Verified via check-llvm in build with AMDGPU, AArch64, and X86 targets.
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@llvm/pr-subscribers-llvm-globalisel, the bot seems to have trouble, so pinging manually |
Maetveis
commented
Oct 7, 2025
| MemDesc(LLT MemoryTy, uint64_t AlignInBits, AtomicOrdering Ordering) | ||
| : MemoryTy(MemoryTy), AlignInBits(AlignInBits), Ordering(Ordering) {} | ||
| MemDesc(LLT MemoryTy, uint64_t AlignInBits, AtomicOrdering Ordering, | ||
| AtomicOrdering FailureOrdering) |
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I was thinking of adding a default value of AtomicOrdering::NotAtomic to FailureOrdering, but I decided that being explicit might be better.
I don't feel strongly about this though. Without the default its possible this pr breaks downstream forks.
arsenm
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Oct 7, 2025
svkeerthy
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Oct 9, 2025
The `cmpxchg` instruction has two memory orders, one for success and one for failure. Prior to this patch `LegalityQuery` only exposed a single memory order, that of the success case. This meant that it was not generally possible to legalize `cmpxchg` instructions based on their memory orders. Add a `FailureOrdering` field to `LegalityQuery::MemDesc`; it is only set for `cmpxchg` instructions, otherwise it is `NotAtomic`. I didn't rename `Ordering` to `SuccessOrdering` or similar to avoid breaking changes for out of tree targets. The new field does not increase `sizeof(MemDesc)`, it falls into previous padding bits due to alignment, so I'd expect there to be no performance impact for this change. Verified no breakage via check-llvm in build with AMDGPU, AArch64, and X86 targets enabled.
clingfei
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that referenced
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Oct 10, 2025
…2284) The `cmpxchg` instruction has two memory orders, one for success and one for failure. Prior to this patch `LegalityQuery` only exposed a single memory order, that of the success case. This meant that it was not generally possible to legalize `cmpxchg` instructions based on their memory orders. Add a `FailureOrdering` field to `LegalityQuery::MemDesc`; it is only set for `cmpxchg` instructions, otherwise it is `NotAtomic`. I didn't rename `Ordering` to `SuccessOrdering` or similar to avoid breaking changes for out of tree targets. The new field does not increase `sizeof(MemDesc)`, it falls into previous padding bits due to alignment, so I'd expect there to be no performance impact for this change. Verified no breakage via check-llvm in build with AMDGPU, AArch64, and X86 targets enabled.
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The
cmpxchginstruction has two memory orders, one for success and one for failure.Prior to this patch LegalityQuery only exposed a single memory order, that of the success case. This meant that it was not generally possible to legalize
cmpxchginstructions based on their memory orders.Add a
FailureOrderingfield toLegalityQuery::MemDesc, it is only set forcmpxchginstructions, otherwise it isNotAtomic. I didn't renameOrderingtoSuccessOrderingor similar to avoid breaking changes for out of tree targets.The new field does not increase
sizeof(MemDesc), it falls into previous padding bits due to alignment, so I'd expect there to be no performance impact for this change.Verified via check-llvm in build with AMDGPU, AArch64, and X86 targets enabled.