Skip to content

[RISCV] Rename atomic instructions to remove underscore between AQ and RL. NFC #162321

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Oct 7, 2025
+49 −48
Merged

[RISCV] Rename atomic instructions to remove underscore between AQ and RL. NFC #162321

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -166,7 +166,7 @@ static unsigned getLRForRMW32(AtomicOrdering Ordering,
return RISCV::LR_W;
return RISCV::LR_W_AQ;
case AtomicOrdering::SequentiallyConsistent:
return RISCV::LR_W_AQ_RL;
return RISCV::LR_W_AQRL;
}
}

Expand Down Expand Up @@ -210,7 +210,7 @@ static unsigned getLRForRMW64(AtomicOrdering Ordering,
return RISCV::LR_D;
return RISCV::LR_D_AQ;
case AtomicOrdering::SequentiallyConsistent:
return RISCV::LR_D_AQ_RL;
return RISCV::LR_D_AQRL;
}
}

Expand Down
28 changes: 14 additions & 14 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,10 +24,10 @@ class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
}

multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
def "" : LR_r<0, 0, funct3, opcodestr>;
def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
def "" : LR_r<0, 0, funct3, opcodestr>;
def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
def _AQRL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
Expand All @@ -37,10 +37,10 @@ class SC_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
opcodestr, "$rd, $rs2, $rs1">;

multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> {
def "" : SC_r<0, 0, funct3, opcodestr>;
def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">;
def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">;
def _AQ_RL : SC_r<1, 1, funct3, opcodestr # ".aqrl">;
def "" : SC_r<0, 0, funct3, opcodestr>;
def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">;
def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">;
def _AQRL : SC_r<1, 1, funct3, opcodestr # ".aqrl">;
}

let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
Expand All @@ -50,10 +50,10 @@ class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
opcodestr, "$rd, $rs2, $rs1">;

multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
def _AQRL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -198,9 +198,9 @@ let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in {
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
!cast<RVInst>(BaseInst#"_RL"), vt>;
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
!cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
!cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
}
let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -49,10 +49,10 @@ class AMO_cas<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr,

multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
DAGOperand RC> {
def "" : AMO_cas<funct5, 0, 0, funct3, opcodestr, RC>;
def _AQ : AMO_cas<funct5, 1, 0, funct3, opcodestr # ".aq", RC>;
def _RL : AMO_cas<funct5, 0, 1, funct3, opcodestr # ".rl", RC>;
def _AQ_RL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>;
def "" : AMO_cas<funct5, 0, 0, funct3, opcodestr, RC>;
def _AQ : AMO_cas<funct5, 1, 0, funct3, opcodestr # ".aq", RC>;
def _RL : AMO_cas<funct5, 0, 1, funct3, opcodestr # ".rl", RC>;
def _AQRL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>;
}

let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
Expand Down Expand Up @@ -86,11 +86,11 @@ multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr),
(vt GPR:$cmp),
(vt GPR:$new)),
(!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>;
def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr),
(vt GPR:$cmp),
(vt GPR:$new)),
(!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>;
} // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds)
let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in {
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
Expand Down
9 changes: 5 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,14 +30,15 @@ class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
opcodestr, "$rs2, $rs1"> {
let rd = 0;
}

multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {
def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
def _AQRL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
}

multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
def _AQRL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
}

//===----------------------------------------------------------------------===//
Expand Down
44 changes: 22 additions & 22 deletions llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -126,19 +126,19 @@ amomaxu.d.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W lr.w t0, (t1)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ lr.w.aq t1, (t2)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_RL lr.w.rl t2, (t3)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQRL lr.w.aqrl t3, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W sc.w t6, t5, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQRL sc.w.aqrl t3, t2, (t1)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D lr.d t0, (t1)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ lr.d.aq t1, (t2)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_RL lr.d.rl t2, (t3)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQRL lr.d.aqrl t3, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D sc.d t6, t5, (t4)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1)
# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQRL sc.d.aqrl t3, t2, (t1)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4)
Expand Down Expand Up @@ -166,15 +166,15 @@ amomaxu.d.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4)
Expand Down Expand Up @@ -202,15 +202,15 @@ amomaxu.d.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4)
# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3)

# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP
Expand Down