[InstrRef][AArch64]Add Target hooks for InstrRef on AArch64 #162327
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Accordint to llvm/docs/InstrRefDebugInfo.md, to support proper instruction. referecing on any platform, the target specific TargetInstrInfo::isLoadFromStackSlotPostFE and TargetInstrInfo::isStoreToStackSlotPostFE are needed to be implemented for the Instruction Reference-based LiveDebugValues pass to identify spill and restore instructions. This patch implements the AArch64 versions of those functions. Namely, AArch64InstrInfo::isLoadFromStackSlotPostFE and AArch64InstrInfo::isStoreToStackSlotPostFE.
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@llvm/pr-subscribers-backend-aarch64 Author: Shubham Sandeep Rastogi (rastogishubham) ChangesAccordint to llvm/docs/InstrRefDebugInfo.md, to support proper instruction. referecing on any platform, the target specific TargetInstrInfo::isLoadFromStackSlotPostFE and This patch implements the AArch64 versions of those functions. Namely, AArch64InstrInfo::isLoadFromStackSlotPostFE and Patch is 2.73 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/162327.diff 178 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index b8761d971a67d..20efc2b8884c2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2357,11 +2357,10 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}
-Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameLoadOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRBui:
@@ -2370,22 +2369,26 @@ Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case AArch64::LDRDui:
case AArch64::LDRQui:
case AArch64::LDR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
-
return 0;
}
-Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameStoreOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRBui:
@@ -2394,16 +2397,55 @@ Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
return 0;
}
+Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
+ return Reg;
+
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return 1;
+ }
+ }
+ return Register();
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
+ if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+ return Reg;
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return 1;
+ }
+ }
+ return Register();
+}
+
/// Check all MachineMemOperands for a hint to suppress pairing.
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 179574a73aa01..44863eb2f6d95 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -205,6 +205,15 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
+ /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ Register isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
+ Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
/// Does this instruction set its full destination register to zero?
static bool isGPRZero(const MachineInstr &MI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index 1fe63c9be8c62..be51210882eaa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -89,23 +89,23 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -113,9 +113,9 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -216,23 +216,23 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -240,9 +240,9 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -343,23 +343,23 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_release_acquire:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -367,9 +367,9 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -470,23 +470,23 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -494,9 +494,9 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -580,22 +580,22 @@ define void @atomic_load_relaxed(i64, i64, ptr %p, ptr %p2) {
; CHECK-OUTLINE-LLSC-O0-LABEL: atomic_load_relaxed:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x4, x2
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, xzr
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_relax
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x3]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -690,17 +690,17 @@ define i128 @val_compare_and_swap_return(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_return:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index e6bf3ab674717..3f51ec747182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -56,10 +56,10 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -133,10 +133,10 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov x8, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w1, [x8]
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
@@ -211,10 +211,10 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -285,10 +285,10 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: mov x1, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_relax
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: ...
[truncated]
|
|
@llvm/pr-subscribers-llvm-globalisel Author: Shubham Sandeep Rastogi (rastogishubham) ChangesAccordint to llvm/docs/InstrRefDebugInfo.md, to support proper instruction. referecing on any platform, the target specific TargetInstrInfo::isLoadFromStackSlotPostFE and This patch implements the AArch64 versions of those functions. Namely, AArch64InstrInfo::isLoadFromStackSlotPostFE and Patch is 2.73 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/162327.diff 178 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index b8761d971a67d..20efc2b8884c2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2357,11 +2357,10 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}
-Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameLoadOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRBui:
@@ -2370,22 +2369,26 @@ Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case AArch64::LDRDui:
case AArch64::LDRQui:
case AArch64::LDR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
-
return 0;
}
-Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameStoreOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRBui:
@@ -2394,16 +2397,55 @@ Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
- break;
}
return 0;
}
+Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameStoreOpcode(MI.getOpcode())) {
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
+ return Reg;
+
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return 1;
+ }
+ }
+ return Register();
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (isFrameLoadOpcode(MI.getOpcode())) {
+ if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+ return Reg;
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return 1;
+ }
+ }
+ return Register();
+}
+
/// Check all MachineMemOperands for a hint to suppress pairing.
bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 179574a73aa01..44863eb2f6d95 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -205,6 +205,15 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
+ /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ Register isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
+ Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const override;
+
/// Does this instruction set its full destination register to zero?
static bool isGPRZero(const MachineInstr &MI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index 1fe63c9be8c62..be51210882eaa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -89,23 +89,23 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -113,9 +113,9 @@ define void @val_compare_and_swap(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -216,23 +216,23 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic_seqcst:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -240,9 +240,9 @@ define void @val_compare_and_swap_monotonic_seqcst(ptr %p, i128 %oldval, i128 %n
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -343,23 +343,23 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_release_acquire:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -367,9 +367,9 @@ define void @val_compare_and_swap_release_acquire(ptr %p, i128 %oldval, i128 %ne
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -470,23 +470,23 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_monotonic:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq_rel
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x0, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x8
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x0]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -494,9 +494,9 @@ define void @val_compare_and_swap_monotonic(ptr %p, i128 %oldval, i128 %newval)
; CHECK-CAS-O0: // %bb.0:
; CHECK-CAS-O0-NEXT: sub sp, sp, #16
; CHECK-CAS-O0-NEXT: .cfi_def_cfa_offset 16
-; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-CAS-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-CAS-O0-NEXT: mov x1, x5
-; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Folded Reload
+; CHECK-CAS-O0-NEXT: ldr x5, [sp, #8] // 8-byte Reload
; CHECK-CAS-O0-NEXT: // kill: def $x2 killed $x2 def $x2_x3
; CHECK-CAS-O0-NEXT: mov x3, x5
; CHECK-CAS-O0-NEXT: // kill: def $x4 killed $x4 def $x4_x5
@@ -580,22 +580,22 @@ define void @atomic_load_relaxed(i64, i64, ptr %p, ptr %p2) {
; CHECK-OUTLINE-LLSC-O0-LABEL: atomic_load_relaxed:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x4, x2
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x3, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, xzr
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_relax
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x3, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: // implicit-def: $q0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[0], x0
; CHECK-OUTLINE-LLSC-O0-NEXT: mov v0.d[1], x1
; CHECK-OUTLINE-LLSC-O0-NEXT: str q0, [x3]
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
@@ -690,17 +690,17 @@ define i128 @val_compare_and_swap_return(ptr %p, i128 %oldval, i128 %newval) {
; CHECK-OUTLINE-LLSC-O0-LABEL: val_compare_and_swap_return:
; CHECK-OUTLINE-LLSC-O0: // %bb.0:
; CHECK-OUTLINE-LLSC-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-LLSC-O0-NEXT: .cfi_offset w30, -16
-; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-OUTLINE-LLSC-O0-NEXT: str x0, [sp, #8] // 8-byte Spill
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x0, x2
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x1, x3
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x2, x4
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x4, [sp, #8] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: mov x3, x5
; CHECK-OUTLINE-LLSC-O0-NEXT: bl __aarch64_cas16_acq
-; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-OUTLINE-LLSC-O0-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-OUTLINE-LLSC-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-LLSC-O0-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index e6bf3ab674717..3f51ec747182a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -56,10 +56,10 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -133,10 +133,10 @@ define i32 @val_compare_and_swap_from_load(ptr %p, i32 %cmp, ptr %pnew) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov x8, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w1, [x8]
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
@@ -211,10 +211,10 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov w0, w1
; CHECK-OUTLINE-O0-NEXT: mov w1, w2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
@@ -285,10 +285,10 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) #0 {
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: mov x1, x2
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_relax
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: ...
[truncated]
|
jmorse
reviewed
Oct 8, 2025
| FrameIndex = | ||
| cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue()) | ||
| ->getFrameIndex(); | ||
| return 1; |
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Hmm -- I understand this is how ARM works (versus aarch64), however I think this will run into difficulty with InstrRef. InstrRefBasedLDV::isLocationSpill stores the return value of this function into its Reg reference, which is then used to determine which register is being spilt. That's significant as it determines what value is being transferred onto the stack.
If it's impossible to determine that information this late in compilation, it might be sufficient to just use the earlier clause, those for which isStoreToStackSlot returns a register?
(Similarly for isLoadFromStackSlotPostFE).
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Accordint to llvm/docs/InstrRefDebugInfo.md, to support proper instruction. referecing on any platform, the target specific
TargetInstrInfo::isLoadFromStackSlotPostFEandTargetInstrInfo::isStoreToStackSlotPostFEare needed to be implemented for the Instruction Reference-based LiveDebugValues pass to identify spill and restore instructions.This patch implements the AArch64 versions of those functions. Namely,
AArch64InstrInfo::isLoadFromStackSlotPostFEandAArch64InstrInfo::isStoreToStackSlotPostFE.