-
Notifications
You must be signed in to change notification settings - Fork 15.2k
[IR] Mark vector intrinsics speculatable #162334
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Merged
Merged
Changes from all commits
Commits
Show all changes
7 commits
Select commit
Hold shift + click to select a range
e069e97
[LICM] Pre-commit test for speculatable vector-intrinsics
artagnon 8732fbc
[IR] Mark vector intrinsics speculatable, willreturn
artagnon 5a86092
[Intrinsics] InstWillReturn implied
artagnon ab7adc5
[Intrinsics] Mark more speculatable
artagnon 633bd53
[clang/CodeGen] Update remaining tests
artagnon f60f1ef
[Intrinsics] Integer div/rem not speculatable
artagnon 1dcf6ff
[LICM] Test update
artagnon File filter
Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
There are no files selected for viewing
344 changes: 172 additions & 172 deletions
344
clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
Large diffs are not rendered by default.
Oops, something went wrong.
344 changes: 172 additions & 172 deletions
344
clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_st1_vnum.c
Large diffs are not rendered by default.
Oops, something went wrong.
192 changes: 96 additions & 96 deletions
192
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1.c
Large diffs are not rendered by default.
Oops, something went wrong.
192 changes: 96 additions & 96 deletions
192
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ldnt1.c
Large diffs are not rendered by default.
Oops, something went wrong.
192 changes: 96 additions & 96 deletions
192
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1.c
Large diffs are not rendered by default.
Oops, something went wrong.
192 changes: 96 additions & 96 deletions
192
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_stnt1.c
Large diffs are not rendered by default.
Oops, something went wrong.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,176 @@ | ||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 | ||
; RUN: opt -S -passes='loop-mssa(licm)' -verify-memoryssa %s | FileCheck %s | ||
|
||
define i32 @reduce_umax(<2 x i32> %inv, i1 %c) { | ||
; CHECK-LABEL: define i32 @reduce_umax( | ||
; CHECK-SAME: <2 x i32> [[INV:%.*]], i1 [[C:%.*]]) { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: [[REDUCE_UMAX:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[INV]]) | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[REDUCE_UMAX]] | ||
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false | ||
; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ] | ||
; CHECK-NEXT: ret i32 [[IV_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
|
||
loop: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ] | ||
%iv.next = add i32 %iv, 1 | ||
br i1 %c, label %cond.true, label %exit | ||
|
||
cond.true: | ||
%reduce.umax = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %inv) | ||
%backedge.cond = icmp ult i32 %iv, %reduce.umax | ||
br i1 %backedge.cond, label %loop, label %exit | ||
|
||
exit: | ||
ret i32 %iv | ||
} | ||
|
||
define i32 @vp_umax(<2 x i32> %inv.l, <2 x i32> %inv.r, i1 %c) { | ||
; CHECK-LABEL: define i32 @vp_umax( | ||
; CHECK-SAME: <2 x i32> [[INV_L:%.*]], <2 x i32> [[INV_R:%.*]], i1 [[C:%.*]]) { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: [[VP_UMAX:%.*]] = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> [[INV_L]], <2 x i32> [[INV_R]], <2 x i1> splat (i1 true), i32 2) | ||
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UMAX]], i32 0 | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]] | ||
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C]], i1 [[BACKEDGE_COND]], i1 false | ||
; CHECK-NEXT: br i1 [[OR_COND]], label %[[LOOP]], label %[[EXIT:.*]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[LOOP]] ] | ||
; CHECK-NEXT: ret i32 [[IV_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
|
||
loop: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ] | ||
%iv.next = add i32 %iv, 1 | ||
br i1 %c, label %cond.true, label %exit | ||
|
||
cond.true: | ||
%vp.umax = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %inv.l, <2 x i32> %inv.r, <2 x i1> splat (i1 1), i32 2) | ||
%extract = extractelement <2 x i32> %vp.umax, i32 0 | ||
%backedge.cond = icmp ult i32 %iv, %extract | ||
br i1 %backedge.cond, label %loop, label %exit | ||
|
||
exit: | ||
ret i32 %iv | ||
} | ||
|
||
define i32 @vp_udiv(<2 x i32> %inv.q, <2 x i32> %inv.d, i1 %c) { | ||
; CHECK-LABEL: define i32 @vp_udiv( | ||
; CHECK-SAME: <2 x i32> [[INV_Q:%.*]], <2 x i32> [[INV_D:%.*]], i1 [[C:%.*]]) { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ] | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]] | ||
; CHECK: [[COND_TRUE]]: | ||
; CHECK-NEXT: [[VP_UDIV:%.*]] = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> [[INV_Q]], <2 x i32> [[INV_D]], <2 x i1> splat (i1 true), i32 2) | ||
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_UDIV]], i32 0 | ||
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]] | ||
; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ] | ||
; CHECK-NEXT: ret i32 [[IV_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
|
||
loop: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ] | ||
%iv.next = add i32 %iv, 1 | ||
br i1 %c, label %cond.true, label %exit | ||
|
||
cond.true: | ||
%vp.udiv = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %inv.q, <2 x i32> %inv.d, <2 x i1> splat (i1 1), i32 2) | ||
%extract = extractelement <2 x i32> %vp.udiv, i32 0 | ||
%backedge.cond = icmp ult i32 %iv, %extract | ||
br i1 %backedge.cond, label %loop, label %exit | ||
|
||
exit: | ||
ret i32 %iv | ||
} | ||
|
||
define i32 @vp_load(ptr %inv, i1 %c) { | ||
; CHECK-LABEL: define i32 @vp_load( | ||
; CHECK-SAME: ptr [[INV:%.*]], i1 [[C:%.*]]) { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ] | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]] | ||
; CHECK: [[COND_TRUE]]: | ||
; CHECK-NEXT: [[VP_LOAD:%.*]] = call <2 x i32> @llvm.vp.load.v2i32.p0(ptr [[INV]], <2 x i1> splat (i1 true), i32 2) | ||
; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x i32> [[VP_LOAD]], i32 0 | ||
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV]], [[EXTRACT]] | ||
; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[EXIT]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ] | ||
; CHECK-NEXT: ret i32 [[IV_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
|
||
loop: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ] | ||
%iv.next = add i32 %iv, 1 | ||
br i1 %c, label %cond.true, label %exit | ||
|
||
cond.true: | ||
%vp.load = call <2 x i32> @llvm.vp.load.v2i32(ptr %inv, <2 x i1> splat (i1 1), i32 2) | ||
%extract = extractelement <2 x i32> %vp.load, i32 0 | ||
%backedge.cond = icmp ult i32 %iv, %extract | ||
br i1 %backedge.cond, label %loop, label %exit | ||
|
||
exit: | ||
ret i32 %iv | ||
} | ||
|
||
define i32 @vp_store(<2 x i32> %inv.v, ptr %inv.p, i1 %c) { | ||
; CHECK-LABEL: define i32 @vp_store( | ||
; CHECK-SAME: <2 x i32> [[INV_V:%.*]], ptr [[INV_P:%.*]], i1 [[C:%.*]]) { | ||
; CHECK-NEXT: [[ENTRY:.*]]: | ||
; CHECK-NEXT: br label %[[LOOP:.*]] | ||
; CHECK: [[LOOP]]: | ||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[COND_TRUE:.*]] ] | ||
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 | ||
; CHECK-NEXT: br i1 [[C]], label %[[COND_TRUE]], label %[[EXIT:.*]] | ||
; CHECK: [[COND_TRUE]]: | ||
; CHECK-NEXT: call void @llvm.vp.store.v2i32.p0(<2 x i32> [[INV_V]], ptr [[INV_P]], <2 x i1> splat (i1 true), i32 2) | ||
; CHECK-NEXT: [[BACKEDGE_COND:%.*]] = icmp ult i32 [[IV]], 10 | ||
; CHECK-NEXT: br i1 [[BACKEDGE_COND]], label %[[LOOP]], label %[[EXIT]] | ||
; CHECK: [[EXIT]]: | ||
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], %[[COND_TRUE]] ], [ [[IV]], %[[LOOP]] ] | ||
; CHECK-NEXT: ret i32 [[IV_LCSSA]] | ||
; | ||
entry: | ||
br label %loop | ||
|
||
loop: | ||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %cond.true ] | ||
%iv.next = add i32 %iv, 1 | ||
br i1 %c, label %cond.true, label %exit | ||
|
||
cond.true: | ||
call void @llvm.vp.store.v2i32(<2 x i32> %inv.v, ptr %inv.p, <2 x i1> splat (i1 1), i32 2) | ||
%backedge.cond = icmp ult i32 %iv, 10 | ||
br i1 %backedge.cond, label %loop, label %exit | ||
|
||
exit: | ||
ret i32 %iv | ||
} |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Uh oh!
There was an error while loading. Please reload this page.