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[RISCV] Factor out the core part of LMULWriteResMXVariant. NFC #162347

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Merged
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Oct 7, 2025
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[RISCV] Factor out the core part of LMULWriteResMXVariant. NFC #162347

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36 changes: 24 additions & 12 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Original file line number Diff line number Diff line change
Expand Up @@ -567,9 +567,12 @@ multiclass SiFive7WriteResBase<int VLEN,
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [VCQ, VL],
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred,
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Is this just formatting and adding comments?

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Formatting + comment + adding the non-predicated-variant proc resources argument (i.e. the second appearance of [VCQ, VL]) -- previously LMULWriteResMXVariant always uses the same proc resource for both predicated and non-predicated variant. This patch splits it so that users can customize the resources for non-predicated variant as well.

// Predicated
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
// Not Predicated
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
mx, IsWorstCase>;
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVLDUX8", [VCQ, VL], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVLDOX8", [VCQ, VL], mx, IsWorstCase>;
Expand All @@ -587,9 +590,12 @@ multiclass SiFive7WriteResBase<int VLEN,
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [VCQ, VL],
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred,
// Predicated
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
// Not Predicated
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
mx, IsWorstCase>;
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVLDUX16", [VCQ, VL], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVLDOX16", [VCQ, VL], mx, IsWorstCase>;
Expand All @@ -604,9 +610,12 @@ multiclass SiFive7WriteResBase<int VLEN,
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [VCQ, VL],
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred,
// Predicated
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
// Not Predicated
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
mx, IsWorstCase>;
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVLDUX32", [VCQ, VL], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVLDOX32", [VCQ, VL], mx, IsWorstCase>;
Expand All @@ -621,9 +630,12 @@ multiclass SiFive7WriteResBase<int VLEN,
defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [VCQ, VL],
4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles),
[0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred,
// Predicated
[VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)],
// Not Predicated
[VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)],
mx, IsWorstCase>;
let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVLDUX64", [VCQ, VL], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVLDOX64", [VCQ, VL], mx, IsWorstCase>;
Expand Down
55 changes: 35 additions & 20 deletions llvm/lib/Target/RISCV/RISCVScheduleV.td
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Expand Up @@ -67,42 +67,41 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
// is created similarly if IsWorstCase is true.
multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
list<ProcResourceKind> resources,
int predLat, list<int> predAcquireCycles,
list<int> predReleaseCycles, int noPredLat,
list<int> noPredAcquireCycles,
list<int> noPredReleaseCycles,
string mx, bit IsWorstCase> {
defvar nameMX = name # "_" # mx;

multiclass LMULWriteResVariantImpl<string name, string writeResName, SchedPredicateBase Pred,
list<ProcResourceKind> predResources,
int predLat, list<int> predAcquireCycles,
list<int> predReleaseCycles,
list<ProcResourceKind> noPredResources,
int noPredLat, list<int> noPredAcquireCycles,
list<int> noPredReleaseCycles,
bit IsWorstCase> {
// Define the different behaviors
def nameMX # "_Pred" : SchedWriteRes<resources>{
def writeResName # "_Pred" : SchedWriteRes<predResources>{
let Latency = predLat;
let AcquireAtCycles = predAcquireCycles;
let ReleaseAtCycles = predReleaseCycles;
}
def nameMX # "_NoPred" : SchedWriteRes<resources> {
def writeResName # "_NoPred" : SchedWriteRes<noPredResources> {
let Latency = noPredLat;
let AcquireAtCycles = noPredAcquireCycles;
let ReleaseAtCycles = noPredReleaseCycles;
}

// Define SchedVars
def nameMX # PredSchedVar
: SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>;
def nameMX # NoPredSchedVar
: SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX #"_NoPred")]>;
def writeResName # PredSchedVar
: SchedVar<Pred, [!cast<SchedWriteRes>(NAME # writeResName # "_Pred")]>;
def writeResName # NoPredSchedVar
: SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # writeResName #"_NoPred")]>;
// Allow multiclass to refer to SchedVars -- need to have NAME prefix.
defvar PredSchedVar = !cast<SchedVar>(NAME # nameMX # PredSchedVar);
defvar NoPredSchedVar = !cast<SchedVar>(NAME # nameMX # NoPredSchedVar);
defvar PredSchedVar = !cast<SchedVar>(NAME # writeResName # PredSchedVar);
defvar NoPredSchedVar = !cast<SchedVar>(NAME # writeResName # NoPredSchedVar);

// Tie behavior to predicate
def NAME # nameMX # "_Variant"
def NAME # writeResName # "_Variant"
: SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>;
def : SchedAlias<
!cast<SchedReadWrite>(nameMX),
!cast<SchedReadWrite>(NAME # nameMX # "_Variant")>;
!cast<SchedReadWrite>(writeResName),
!cast<SchedReadWrite>(NAME # writeResName # "_Variant")>;

if IsWorstCase then {
def NAME # name # "_WorstCase_Variant"
Expand All @@ -113,6 +112,22 @@ multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
}
}

multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
list<ProcResourceKind> predResources,
int predLat, list<int> predAcquireCycles,
list<int> predReleaseCycles,
list<ProcResourceKind> noPredResources,
int noPredLat, list<int> noPredAcquireCycles,
list<int> noPredReleaseCycles,
string mx, bit IsWorstCase> {
defm "" : LMULWriteResVariantImpl<name, name # "_" # mx, Pred, predResources,
predLat, predAcquireCycles,
predReleaseCycles, noPredResources,
noPredLat, noPredAcquireCycles,
noPredReleaseCycles,
IsWorstCase>;
}

// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
// SchedMxList variants above. Each multiclass is responsible for defining
Expand Down