[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 #162352
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| Original file line number | Diff line number | Diff line change |
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@@ -10577,6 +10577,67 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, | |
| if (SrcReg2 && !getFoldableImm(SrcReg2, *MRI, CmpValue)) | ||
| return false; | ||
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| const auto optimizeCmpSelect = [&CmpInstr, SrcReg, CmpValue, MRI, | ||
| this]() -> bool { | ||
| if (CmpValue != 0) | ||
| return false; | ||
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| MachineInstr *Def = MRI->getUniqueVRegDef(SrcReg); | ||
| if (!Def || Def->getParent() != CmpInstr.getParent()) | ||
| return false; | ||
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| bool CanOptimize = false; | ||
| MachineOperand *SccDef = | ||
| Def->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr); | ||
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| // For S_OP that set SCC = DST!=0, do the transformation | ||
| // | ||
| // s_cmp_lg_* (S_OP ...), 0 => (S_OP ...) | ||
| if (SccDef && Def->getOpcode() != AMDGPU::S_ADD_I32 && | ||
| Def->getOpcode() != AMDGPU::S_ADD_U32 && | ||
| Def->getOpcode() != AMDGPU::S_ADDC_U32 && | ||
| Def->getOpcode() != AMDGPU::S_SUB_I32 && | ||
| Def->getOpcode() != AMDGPU::S_SUB_U32 && | ||
| Def->getOpcode() != AMDGPU::S_SUBB_U32 && | ||
| Def->getOpcode() != AMDGPU::S_MIN_I32 && | ||
| Def->getOpcode() != AMDGPU::S_MIN_U32 && | ||
| Def->getOpcode() != AMDGPU::S_MAX_I32 && | ||
| Def->getOpcode() != AMDGPU::S_MAX_U32 && | ||
| Def->getOpcode() != AMDGPU::S_ADDK_I32) | ||
| CanOptimize = true; | ||
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| // s_cmp_lg_* is redundant because the SCC input value for S_CSELECT* has | ||
| // the same value that will be calculated by s_cmp_lg_* | ||
| // | ||
| // s_cmp_lg_* (S_CSELECT* (non-zero imm), 0), 0 => (S_CSELECT* (non-zero | ||
| // imm), 0) | ||
| if (Def->getOpcode() == AMDGPU::S_CSELECT_B32 || | ||
| Def->getOpcode() == AMDGPU::S_CSELECT_B64) { | ||
| bool Op1IsNonZeroImm = | ||
| Def->getOperand(1).isImm() && Def->getOperand(1).getImm() != 0; | ||
| bool Op2IsZeroImm = | ||
| Def->getOperand(2).isImm() && Def->getOperand(2).getImm() == 0; | ||
| if (Op1IsNonZeroImm && Op2IsZeroImm) | ||
| CanOptimize = true; | ||
| } | ||
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| if (!CanOptimize) | ||
| return false; | ||
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| for (auto I = std::next(Def->getIterator()), E = CmpInstr.getIterator(); | ||
| I != E; ++I) { | ||
| if (I->modifiesRegister(AMDGPU::SCC, &RI) || | ||
| I->killsRegister(AMDGPU::SCC, &RI)) | ||
| return false; | ||
| } | ||
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Comment on lines
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There was a problem hiding this comment. I don't think you should need to be scanning around for physreg liveness, I don't see other targets doing that here There was a problem hiding this comment.
Scanning for register liveness is also done in the other lambda, optimizeCmpAnd, (line 10752) that is used in optimizeCompareInstr. It is necessary to prevent incorrectly deleting a s_cmp if an there is an intervening definition. In PR #161582, tests were added that requires this scanning. PR #161582 was done to add SCC as an implicit destination of s_quadmask*. Without this fix the scanning would not detect a conflict. |
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| if (SccDef) | ||
| SccDef->setIsDead(false); | ||
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| CmpInstr.eraseFromParent(); | ||
| return true; | ||
| }; | ||
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| const auto optimizeCmpAnd = [&CmpInstr, SrcReg, CmpValue, MRI, | ||
| this](int64_t ExpectedValue, unsigned SrcSize, | ||
| bool IsReversible, bool IsSigned) -> bool { | ||
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@@ -10704,15 +10765,15 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, | |
| case AMDGPU::S_CMP_LG_I32: | ||
| case AMDGPU::S_CMPK_LG_U32: | ||
| case AMDGPU::S_CMPK_LG_I32: | ||
| return optimizeCmpAnd(0, 32, true, false) || optimizeCmpSelect(); | ||
| case AMDGPU::S_CMP_GT_U32: | ||
| case AMDGPU::S_CMPK_GT_U32: | ||
| return optimizeCmpAnd(0, 32, false, false); | ||
| case AMDGPU::S_CMP_GT_I32: | ||
| case AMDGPU::S_CMPK_GT_I32: | ||
| return optimizeCmpAnd(0, 32, false, true); | ||
| case AMDGPU::S_CMP_LG_U64: | ||
| return optimizeCmpAnd(0, 64, true, false) || optimizeCmpSelect(); | ||
| } | ||
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| return false; | ||
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Don't see why the parent would matter, but this also looks untested
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Def and CmpInstr need to have the same parent so that the scan will work.