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[LegalizeTypes] Use GetSplitVector in SplitVec(Res/Op)_PARTIAL_REDUCE_MLA #162513

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Merged
merged 1 commit into from
Oct 9, 2025
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Merged

[LegalizeTypes] Use GetSplitVector in SplitVec(Res/Op)_PARTIAL_REDUCE_MLA #162513

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10 changes: 5 additions & 5 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3416,7 +3416,7 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
SDValue Input2 = N->getOperand(2);

SDValue AccLo, AccHi;
std::tie(AccLo, AccHi) = DAG.SplitVector(Acc, DL);
GetSplitVector(Acc, AccLo, AccHi);
unsigned Opcode = N->getOpcode();

// If the input types don't need splitting, just accumulate into the
Expand All @@ -3429,8 +3429,8 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,

SDValue Input1Lo, Input1Hi;
SDValue Input2Lo, Input2Hi;
std::tie(Input1Lo, Input1Hi) = DAG.SplitVector(Input1, DL);
std::tie(Input2Lo, Input2Hi) = DAG.SplitVector(Input2, DL);
GetSplitVector(Input1, Input1Lo, Input1Hi);
GetSplitVector(Input2, Input2Lo, Input2Hi);
EVT ResultVT = AccLo.getValueType();

Lo = DAG.getNode(Opcode, DL, ResultVT, AccLo, Input1Lo, Input2Lo);
Expand Down Expand Up @@ -4761,8 +4761,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_PARTIAL_REDUCE_MLA(SDNode *N) {

SDLoc DL(N);
SDValue Input1Lo, Input1Hi, Input2Lo, Input2Hi;
std::tie(Input1Lo, Input1Hi) = DAG.SplitVector(N->getOperand(1), DL);
std::tie(Input2Lo, Input2Hi) = DAG.SplitVector(N->getOperand(2), DL);
GetSplitVector(N->getOperand(1), Input1Lo, Input1Hi);
GetSplitVector(N->getOperand(2), Input2Lo, Input2Hi);
unsigned Opcode = N->getOpcode();
EVT ResultVT = Acc.getValueType();

Expand Down