[mlir][amdgpu] Add Inliner interface

[Hardcode84]

All the amdgpu dialect ops can be inlined.

[llvmbot]

@llvm/pr-subscribers-mlir-gpu

@llvm/pr-subscribers-mlir

Author: Ivan Butygin (Hardcode84)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/162873.diff

2 Files Affected:

• (modified) mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp (+11)
• (added) mlir/test/Dialect/AMDGPU/inlining.mlir (+15)

diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
index d5c71905f7b4a..9649f6138e1a1 100644
--- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
+++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
@@ -26,6 +26,7 @@
 #include "mlir/IR/OpImplementation.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/IR/TypeUtilities.h"
+#include "mlir/Transforms/InliningUtils.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/TypeSwitch.h"
@@ -40,6 +41,15 @@ using namespace mlir::amdgpu;
 
 #include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.cpp.inc"
 
+namespace {
+struct AMDGPUInlinerInterface : public DialectInlinerInterface {
+  using DialectInlinerInterface::DialectInlinerInterface;
+  bool isLegalToInline(Operation *, Region *, bool, IRMapping &) const final {
+    return true;
+  }
+};
+} // namespace
+
 void AMDGPUDialect::initialize() {
   addOperations<
 #define GET_OP_LIST
@@ -49,6 +59,7 @@ void AMDGPUDialect::initialize() {
 #define GET_ATTRDEF_LIST
 #include "mlir/Dialect/AMDGPU/IR/AMDGPUAttributes.cpp.inc"
       >();
+  addInterfaces<AMDGPUInlinerInterface>();
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/AMDGPU/inlining.mlir b/mlir/test/Dialect/AMDGPU/inlining.mlir
new file mode 100644
index 0000000000000..522ae00259077
--- /dev/null
+++ b/mlir/test/Dialect/AMDGPU/inlining.mlir
@@ -0,0 +1,15 @@
+// RUN: mlir-opt %s --inline | FileCheck %s
+
+func.func @calee(%arg0 : f32) -> f32 {
+  // CHECK: amdgpu.permlane_swap
+  %0 = amdgpu.permlane_swap %arg0 32 : f32
+  func.return %0 : f32
+}
+
+// CHECK-LABEL: func @caller
+func.func @caller(%arg0 : f32) -> f32 {
+  // CHECK-NOT: call
+  //     CHECK: amdgpu.permlane_swap
+  %0 = call @calee(%arg0) : (f32) -> f32
+  func.return %0 : f32
+}

[krzysz00]

Approved if we get a slightly more detailed commit message pointing out that none of the amdgpu dialect operations can't be inlined.