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[ARM][MVE] Invalid tail predication in LowOverheadLoop pass #163217

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[ARM][MVE] Invalid tail predication in LowOverheadLoop pass #163217

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f050ab5
[ARM][MVE] Invalid tail predication in LowOverheadLoop pass
statham-arm Oct 13, 2025
7dc18e7
Remove special case for MQPRCopy at end
statham-arm Oct 14, 2025
477af29
Add assertion justifying (and checking) the i+3 magic number
statham-arm Oct 14, 2025
0dc637a
git-clang-format
statham-arm Oct 14, 2025
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25 changes: 17 additions & 8 deletions llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -955,8 +955,23 @@ bool LowOverheadLoop::ValidateLiveOuts() {
else if (!isPredicated && retainsOrReduces) {
LLVM_DEBUG(dbgs() << " Unpredicated instruction that retainsOrReduces: " << MI);
return false;
} else if (!isPredicated && MI.getOpcode() != ARM::MQPRCopy)
} else if (!isPredicated)
FalseLanesUnknown.insert(&MI);
else if (int InactiveIdx = findVPTInactiveOperandIdx(MI);
InactiveIdx != -1) {
auto MO = MI.getOperand(InactiveIdx);
SmallPtrSet<MachineInstr *, 2> Defs;
RDI.getGlobalReachingDefs(&MI, MO.getReg(), Defs);
for (auto *Def : Defs) {
if (Def != &MI && FalseLanesUnknown.count(Def)) {
LLVM_DEBUG(dbgs() << " we think this is FalseLanesUnknown: " << MI);
LLVM_DEBUG(dbgs()
<< " because it takes the false lanes of this: " << *Def);
FalseLanesUnknown.insert(&MI);
break;
}
}
}
}

LLVM_DEBUG({
Expand Down Expand Up @@ -1035,13 +1050,7 @@ bool LowOverheadLoop::ValidateLiveOuts() {
SmallVector<MachineInstr *> Worklist(LiveOutMIs.begin(), LiveOutMIs.end());
while (!Worklist.empty()) {
MachineInstr *MI = Worklist.pop_back_val();
if (MI->getOpcode() == ARM::MQPRCopy) {
VMOVCopies.insert(MI);
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So, can we now completely remove VMOVCopies?

(And, not to be part of this patch, but I wonder if the MQPRCopy instruction could also be removed.)

MachineInstr *CopySrc =
RDI.getUniqueReachingMIDef(MI, MI->getOperand(1).getReg());
if (CopySrc)
Worklist.push_back(CopySrc);
} else if (NonPredicated.count(MI) && FalseLanesUnknown.contains(MI)) {
if (NonPredicated.count(MI) && FalseLanesUnknown.contains(MI)) {
LLVM_DEBUG(dbgs() << " Unable to handle live out: " << *MI);
VMOVCopies.clear();
return false;
Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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Expand Up @@ -805,6 +805,19 @@ int llvm::findFirstVPTPredOperandIdx(const MachineInstr &MI) {
return -1;
}

int llvm::findVPTInactiveOperandIdx(const MachineInstr &MI) {
const MCInstrDesc &MCID = MI.getDesc();

for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
if (MCID.operands()[i].OperandType == ARM::OPERAND_VPRED_R) {
assert(MCID.getOperandConstraint(i + 3, MCOI::TIED_TO) != -1 &&
"Operand #3 of VPRED_R is the one tied to the output register");
return i + 3;
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Can we use a named constant for this magic '3'?

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There's no existing set of constant definitions I know of at the moment which tells you what sub-operands a VPRED_R has and which one goes where.

The number of them changed in 9cb8f4d, adding a new one just before the tied operand I'm referring to here – before that commit my function here would have had to return i+2. You can see in that commit that it also has no alternative but to refer to numeric offsets from the first VPRED_R operand, such as the part of the patch that touches ARMDisassembler.cpp.

I could imagine making Tablegen write out some constants of this kind into a header file. The definition of vpred_r in ARMInstrFormats.td assigns a name to each sub-operand in the MIOperandInfo field, so we could write out a giant enum defining constants like ARM::SUBOP_VPRED_R_inactive, and then clean up all the magic numbers in that patch as well as this one. But that seems quite a long way beyond the scope of this change!

On the theory that the main aim of removing magic numbers is to make sure everything is updated correctly when (if) the right number changes, I can add an assert here, which checks that operand i+3 is the one with a TIED_TO constraint. Is that good enough for now?

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Okay, cheers, this seems good enough to me.

}

return -1;
}

ARMVCC::VPTCodes llvm::getVPTInstrPredicate(const MachineInstr &MI,
Register &PredReg) {
int PIdx = findFirstVPTPredOperandIdx(MI);
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/ARM/Thumb2InstrInfo.h
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Expand Up @@ -90,6 +90,9 @@ inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) {
Register PredReg;
return getVPTInstrPredicate(MI, PredReg);
}
// Identify the input operand in an MVE predicated instruction which
// contributes the values of any inactive vector lanes.
int findVPTInactiveOperandIdx(const MachineInstr &MI);

// Recomputes the Block Mask of Instr, a VPT or VPST instruction.
// This rebuilds the block mask of the instruction depending on the predicates
Expand Down
30 changes: 19 additions & 11 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
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Expand Up @@ -309,34 +309,42 @@ body: |
; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = t2LDRHi12 $sp, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r6, dead $cpsr = nsw tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r5, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tLSLri killed renamable $r1, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r3 = t2RSBri killed renamable $r3, 256, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $q0 = MVE_VDUP16 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0
; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r6, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r6 = nuw nsw t2ADDrs killed renamable $r5, killed renamable $r3, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $d0, $d1, $r0, $r1, $r2, $r3, $r6, $r12
; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = MVE_DLSTP_16 renamable $r2
; CHECK-NEXT: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = t2DLS renamable $r6
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK-NEXT: liveins: $lr, $d0, $d1, $r0, $r1, $r2, $r3, $r4, $r6, $r12
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 renamable $r4, 0, 0, $noreg, renamable $lr
; CHECK-NEXT: $d4 = VMOVD killed $d0, 14 /* CC::al */, $noreg
; CHECK-NEXT: $d5 = VMOVD killed $d1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r5, 0, $noreg, $noreg
; CHECK-NEXT: renamable $r5, dead $cpsr = tSUBi8 killed renamable $r5, 8, 14 /* CC::al */, $noreg
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 renamable $r4, 0, 1, renamable $vpr, renamable $lr
; CHECK-NEXT: $q2 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q2
; CHECK-NEXT: renamable $q1 = MVE_VAND killed renamable $q1, renamable $q2, 0, $noreg, renamable $lr, undef renamable $q1
; CHECK-NEXT: $d0 = VMOVD killed $d4, 14 /* CC::al */, $noreg
; CHECK-NEXT: $d1 = VMOVD killed $d5, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r4 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r4, 16, 0, killed $noreg, renamable $lr
; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.3
; CHECK-NEXT: $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, $noreg, undef $q0
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: renamable $r4 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r4, 16, 1, killed renamable $vpr, renamable $lr
; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
; CHECK-NEXT: liveins: $d0, $d1, $r0, $r1, $r2, $r3, $r6, $r12
; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r6, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3, dead $cpsr = nuw nsw tADDi8 killed renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r0 = tADDhirr killed renamable $r0, renamable $r1, 14 /* CC::al */, $noreg
Expand Down
20 changes: 14 additions & 6 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
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Expand Up @@ -447,20 +447,28 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK-NEXT: renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1 (align 4):
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $lr, $q0, $r0
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK-NEXT: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, killed renamable $q1
; CHECK-NEXT: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, killed $noreg, $noreg
; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
; CHECK-NEXT: MVE_VPST 4, implicit $vpr
; CHECK-NEXT: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, killed renamable $q1
; CHECK-NEXT: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
; CHECK-NEXT: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, $noreg, killed renamable $q0
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
Expand Down
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