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[PowerPC] Use rldimi/rlwimi to optimize build_vector #67640

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Leverage rldimi/rlwimi instructions to generate better code for BUILD_VECTOR:

  • For v16i8, four groups of (i8 << 24) | (i8 << 16) | (i8 << 8) | i8 to construct a vector.
  • For v8i16, four groups of (i16 << 16) | i16 to construct a vector.

We already have patterns for v4i32 and v2i64 construction.

Migrated from https://reviews.llvm.org/D94467

Leverage rldimi/rlwimi instructions to generate better code for BUILD_VECTOR:

- For v16i8, four groups of (i8 << 24) | (i8 << 16) | (i8 << 8) | i8 to construct a vector.
- For v8i16, four groups of (i16 << 16) | i16 to construct a vector.

We already have patterns for v4i32 and v2i64 construction.
Comment on lines -243 to -261
; P9LE-NEXT: sldi 4, 4, 1
; P9LE-NEXT: li 7, 16
; P9LE-NEXT: add 6, 3, 4
; P9LE-NEXT: lxsihzx 4, 3, 4
; P9LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; P9LE-NEXT: lxsihzx 2, 6, 7
; P9LE-NEXT: li 6, 0
; P9LE-NEXT: addi 3, 3, .LCPI2_0@toc@l
; P9LE-NEXT: mtvsrd 3, 6
; P9LE-NEXT: lxv 0, 0(3)
; P9LE-NEXT: li 3, 0
; P9LE-NEXT: vmrghh 4, 3, 4
; P9LE-NEXT: vmrghh 2, 3, 2
; P9LE-NEXT: vsplth 3, 3, 3
; P9LE-NEXT: xxmrglw 3, 4, 3
; P9LE-NEXT: xxperm 3, 2, 0
; P9LE-NEXT: xxspltw 2, 3, 2
; P9LE-NEXT: vadduwm 2, 3, 2
; P9LE-NEXT: vextuwrx 3, 3, 2
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Some of these code should be dead. I tried opt on it, the loop is gone, and then use current llc, they're removed.

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Why? What is the purpose of a codegen test case that doesn't show the desired codegen?

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This may be more generally useful (i.e. in the target independent DAG combiner).

Comment on lines -243 to -261
; P9LE-NEXT: sldi 4, 4, 1
; P9LE-NEXT: li 7, 16
; P9LE-NEXT: add 6, 3, 4
; P9LE-NEXT: lxsihzx 4, 3, 4
; P9LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; P9LE-NEXT: lxsihzx 2, 6, 7
; P9LE-NEXT: li 6, 0
; P9LE-NEXT: addi 3, 3, .LCPI2_0@toc@l
; P9LE-NEXT: mtvsrd 3, 6
; P9LE-NEXT: lxv 0, 0(3)
; P9LE-NEXT: li 3, 0
; P9LE-NEXT: vmrghh 4, 3, 4
; P9LE-NEXT: vmrghh 2, 3, 2
; P9LE-NEXT: vsplth 3, 3, 3
; P9LE-NEXT: xxmrglw 3, 4, 3
; P9LE-NEXT: xxperm 3, 2, 0
; P9LE-NEXT: xxspltw 2, 3, 2
; P9LE-NEXT: vadduwm 2, 3, 2
; P9LE-NEXT: vextuwrx 3, 3, 2
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Why? What is the purpose of a codegen test case that doesn't show the desired codegen?

SDLoc dl(Op);

// There are already patterns for v4i32 and v2i64 construction.
if (VT == MVT::v16i8 || VT == MVT::v8i16) {
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Please flip the condition and make this an early exit.

for (int i = 0; i < 4; ++i) {
for (int j = 0; j < EltsFor32; ++j) {
SDValue Elt = LittleEndian
? Op.getOperand(i * EltsFor32 + EltsFor32 - j - 1)
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These expressions are far from obvious. Please initialize variables with these expressions with comments explaining the expressions and then use the variables. The reader should not be forced to work out the details of this math without context.

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