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[DAG] Canonicalize zero_extend to sign_extend based on target preference #70671

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[DAG] Canonicalize zero_extend to sign_extend based on target preference #70671

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11 changes: 10 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13481,7 +13481,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
if (SDValue V = foldSextSetcc(N))
return V;

// fold (sext x) -> (zext x) if the sign bit is known zero.
// fold (sext x) -> (zext x) if the sign bit is known zero, and that
// is what the target prefers.
if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
(!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
DAG.SignBitIsZero(N0))
Expand Down Expand Up @@ -13825,6 +13826,14 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC);
}

// fold (zext x) -> (sext x) if the sign bit is known zero, and
// that is what the target prefers.
if (TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)) &&
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0);


// (zext (shl (zext x), cst)) -> (shl (zext x), cst)
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
!TLI.isZExtFree(N0, VT)) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -2419,7 +2419,7 @@ bool TargetLowering::SimplifyDemandedBits(
Known = Known.sext(BitWidth);

// If the sign bit is known zero, convert this to a zero extend.
if (Known.isNonNegative()) {
if (Known.isNonNegative() && !isSExtCheaperThanZExt(SrcVT, VT)) {
unsigned Opc =
IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
Expand Down