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[mlir][docs] Fix a broken passes documentation #77402

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Merged
merged 1 commit into from
Jan 9, 2024

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@sott0n sott0n commented Jan 9, 2024

  • Add EmitC passes into Pass.md
  • Modify header level of the pass description to under the LegalizeVectorStorage pass

@sott0n sott0n marked this pull request as ready for review January 9, 2024 02:15
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llvmbot commented Jan 9, 2024

@llvm/pr-subscribers-mlir

@llvm/pr-subscribers-mlir-sve

Author: Kohei Yamaguchi (sott0n)

Changes
  • Add EmitC passes into Pass.md
  • Modify header level of the pass description to under the LegalizeVectorStorage pass

Full diff: https://github.com/llvm/llvm-project/pull/77402.diff

2 Files Affected:

  • (modified) mlir/docs/Passes.md (+4)
  • (modified) mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td (+2-2)
diff --git a/mlir/docs/Passes.md b/mlir/docs/Passes.md
index 66e2dc077f9854..ee7d47cc022723 100644
--- a/mlir/docs/Passes.md
+++ b/mlir/docs/Passes.md
@@ -40,6 +40,10 @@ This document describes the available MLIR passes and their contracts.
 
 [include "AsyncPasses.md"]
 
+## 'emitc' Dialect Passes
+
+[include "EmitCPasses.md"]
+
 ## 'func' Dialect Passes
 
 [include "FuncPasses.md"]
diff --git a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td
index d7cb309db5253e..b9b06cec1f9779 100644
--- a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td
+++ b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td
@@ -21,7 +21,7 @@ def LegalizeVectorStorage
 
     This pass currently addresses two issues.
 
-    ## Loading and storing predicate types
+    #### Loading and storing predicate types
 
     It is only legal to load/store predicate types equal to (or greater than) a
     full predicate register, which in MLIR is `vector<[16]xi1>`. Smaller
@@ -49,7 +49,7 @@ def LegalizeVectorStorage
     %reload = arm_sve.convert_from_svbool %reload_svbool : vector<[4]xi1>
     ```
 
-    ## Relax alignments for SVE vector allocas
+    #### Relax alignments for SVE vector allocas
 
     The storage for SVE vector types only needs to have an alignment that
     matches the element type (for example 4 byte alignment for `f32`s). However,

@banach-space banach-space requested a review from MacDue January 9, 2024 08:19
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These changes LGTM, thanks!

@sott0n
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sott0n commented Jan 9, 2024

@banach-space @MacDue Thank you for your review! Could you land it?

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MacDue commented Jan 9, 2024

@banach-space @MacDue Thank you for your review! Could you land it?

Sure 👍

@MacDue MacDue merged commit d5985d4 into llvm:main Jan 9, 2024
@sott0n sott0n deleted the fix-mlir-docs branch January 17, 2024 04:47
justinfargnoli pushed a commit to justinfargnoli/llvm-project that referenced this pull request Jan 28, 2024
- Add EmitC passes into Pass.md
- Modify header level of the pass description to under the
`LegalizeVectorStorage` pass
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4 participants