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AMDGPU: Expand remaining system atomic operations #80798

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AMDGPU: Expand remaining system atomic operations #80798

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25 changes: 18 additions & 7 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16018,7 +16018,8 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
SSID == SyncScope::System ||
SSID == RMW->getContext().getOrInsertSyncScopeID("one-as");

switch (RMW->getOperation()) {
auto Op = RMW->getOperation();
switch (Op) {
case AtomicRMWInst::FAdd: {
Type *Ty = RMW->getType();

Expand Down Expand Up @@ -16096,19 +16097,29 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {

return AtomicExpansionKind::CmpXChg;
}
case AtomicRMWInst::FMin:
case AtomicRMWInst::FMax:
case AtomicRMWInst::Min:
case AtomicRMWInst::Xchg:
case AtomicRMWInst::Add:
// PCIe supports add and xchg for system atomics.
break;
case AtomicRMWInst::Sub:
case AtomicRMWInst::And:
case AtomicRMWInst::Or:
case AtomicRMWInst::Xor:
case AtomicRMWInst::Max:
case AtomicRMWInst::Min:
case AtomicRMWInst::UMax:
case AtomicRMWInst::UMin:
case AtomicRMWInst::UMax: {
case AtomicRMWInst::FMin:
case AtomicRMWInst::FMax:
case AtomicRMWInst::UIncWrap:
case AtomicRMWInst::UDecWrap: {
if (AMDGPU::isFlatGlobalAddrSpace(AS) ||
AS == AMDGPUAS::BUFFER_FAT_POINTER) {
if (RMW->getType()->isFloatTy() &&
if (AtomicRMWInst::isFPOperation(Op) &&
unsafeFPAtomicsDisabled(RMW->getFunction()))
return AtomicExpansionKind::CmpXChg;

// Always expand system scope min/max atomics.
// Always expand system scope atomics.
if (HasSystemScope)
return AtomicExpansionKind::CmpXChg;
}
Expand Down
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