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[AMDGPU] Try decoding instructions longest first. NFCI. #82014

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Merged
merged 2 commits into from
Feb 20, 2024
Merged

[AMDGPU] Try decoding instructions longest first. NFCI. #82014

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a1177d3
[AMDGPU] Try decoding instructions longest first. NFCI.
jayfoad Feb 16, 2024
abf91f2
Merge remote-tracking branch 'origin/main' into decoder-longest-first
jayfoad Feb 20, 2024
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84 changes: 42 additions & 42 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -595,6 +595,48 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Res)
break;
}

if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) {
Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS);
if (Res)
break;
}

if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS);
if (Res)
break;
}

Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI,
QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI,
QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS);
if (Res)
break;
}

// Reinitialize Bytes as DPP64 could have eaten too much
Expand Down Expand Up @@ -632,48 +674,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
Address, CS);
if (Res)
break;

if (Bytes.size() < 4) break;
const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;

if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) {
Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS);
if (Res)
break;
}

if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS);
if (Res)
break;
}

Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS);
if (Res) break;

Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS);
if (Res) break;

Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
if (Res) break;

Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS);
if (Res)
break;

Res = tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS);
} while (false);

if (Res && AMDGPU::isMAC(MI.getOpcode())) {
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2571,11 +2571,13 @@ multiclass SOPP_Real_32_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :

multiclass SOPP_Real_With_Relaxation_gfx12<bits<7> op> {
defm "" : SOPP_Real_32_gfx12<op>;
let isCodeGenOnly = 1 in
defm _pad_s_nop : SOPP_Real_64_gfx12<op>;
}

multiclass SOPP_Real_With_Relaxation_gfx11<bits<7> op> {
defm "" : SOPP_Real_32_gfx11<op>;
let isCodeGenOnly = 1 in
defm _pad_s_nop : SOPP_Real_64_gfx11<op>;
}

Expand Down Expand Up @@ -2697,6 +2699,7 @@ multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :
//relaxation for insts with no operands not implemented
multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> {
defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
let isCodeGenOnly = 1 in
defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
}

Expand Down