[PowerPC] Retire PPCExpandISel pass #84289

bzEq · 2024-03-07T09:04:27Z

We can decide whether to expand isel or not in instruction selection pass and early-if-conversion pass. The transformation implemented in PPCExpandISel can be retired considering PPC backend doesn't generate isel instructions post-RA.
Also if we are seeking performant branch-or-isel decision, we can turn to selectoptimize pass.

llvmbot · 2024-03-07T09:04:57Z

@llvm/pr-subscribers-backend-powerpc

Author: Kai Luo (bzEq)

Changes

Patch is 20.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/84289.diff

5 Files Affected:

(modified) llvm/lib/Target/PowerPC/PPCExpandISEL.cpp (+3-4)
(modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+3-1)
(modified) llvm/test/CodeGen/PowerPC/crbits.ll (+15-17)
(modified) llvm/test/CodeGen/PowerPC/optcmp.ll (+3-5)
(modified) llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll (+124-110)

diff --git a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp
index 4c74e82cf04125..b2947c2e93e7d7 100644
--- a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp
+++ b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp
@@ -36,10 +36,9 @@ STATISTIC(NumFolded, "Number of ISEL instructions folded");
 // instruction on all PPC targets. Otherwise, if the user set option
 // -misel or the platform supports ISEL by default, still generate the
 // ISEL instruction, else expand it.
-static cl::opt<bool>
-    GenerateISEL("ppc-gen-isel",
-                 cl::desc("Enable generating the ISEL instruction."),
-                 cl::init(true), cl::Hidden);
+cl::opt<bool> GenerateISEL("ppc-gen-isel",
+                           cl::desc("Enable generating the ISEL instruction."),
+                           cl::init(true), cl::Hidden);
 
 namespace {
 class PPCExpandISEL : public MachineFunctionPass {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 68c80dd9aa5c76..f5e53e46f161a6 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -158,6 +158,8 @@ constexpr uint64_t AIXSmallTlsPolicySizeLimit = 32751;
 // FIXME: Remove this once the bug has been fixed!
 extern cl::opt<bool> ANDIGlueBug;
 
+extern cl::opt<bool> GenerateISEL;
+
 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
                                      const PPCSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
@@ -12798,7 +12800,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   MachineFunction *F = BB->getParent();
   MachineRegisterInfo &MRI = F->getRegInfo();
 
-  if (Subtarget.hasISEL() &&
+  if ((Subtarget.hasISEL() && GenerateISEL) &&
       (MI.getOpcode() == PPC::SELECT_CC_I4 ||
        MI.getOpcode() == PPC::SELECT_CC_I8 ||
        MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8)) {
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
index a682f69a2ceb78..1e95b8c49213d8 100644
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -30,16 +30,16 @@ define zeroext i1 @test1(float %v1, float %v2) #0 {
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
-; CHECK-NO-ISEL-NEXT:    li 3, 1
+; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
-; CHECK-NO-ISEL-NEXT:    crnor 21, 7, 1
-; CHECK-NO-ISEL-NEXT:    crnand 20, 20, 21
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB0_1
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB0_1: # %entry
-; CHECK-NO-ISEL-NEXT:    li 3, 0
+; CHECK-NO-ISEL-NEXT:    bclr 4, 20, 0
+; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT:    crnor 20, 7, 1
+; CHECK-NO-ISEL-NEXT:    bclr 4, 20, 0
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test1:
@@ -81,16 +81,15 @@ define zeroext i1 @test2(float %v1, float %v2) #0 {
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
-; CHECK-NO-ISEL-NEXT:    li 3, 1
+; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
 ; CHECK-NO-ISEL-NEXT:    crnor 21, 7, 1
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB1_1
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB1_1: # %entry
-; CHECK-NO-ISEL-NEXT:    li 3, 0
+; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test2:
@@ -134,7 +133,7 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
-; CHECK-NO-ISEL-NEXT:    li 3, 1
+; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
@@ -142,10 +141,9 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
 ; CHECK-NO-ISEL-NEXT:    cmpwi 5, -2
 ; CHECK-NO-ISEL-NEXT:    crandc 21, 21, 2
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB2_1
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB2_1: # %entry
-; CHECK-NO-ISEL-NEXT:    li 3, 0
+; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test3:
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
index bc265c646d471e..641b83ab3d83e8 100644
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -336,12 +336,10 @@ define signext i64 @fooct(i64 signext %a, i64 signext %b, ptr nocapture %c) #0 {
 ; CHECK-NO-ISEL-NEXT:    and 6, 6, 7
 ; CHECK-NO-ISEL-NEXT:    mulld 6, 6, 9
 ; CHECK-NO-ISEL-NEXT:    rldicl. 6, 6, 8, 56
-; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB10_2
-; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 4, 0
-; CHECK-NO-ISEL-NEXT:    b .LBB10_2
-; CHECK-NO-ISEL-NEXT:  .LBB10_2: # %entry
 ; CHECK-NO-ISEL-NEXT:    std 6, 0(5)
+; CHECK-NO-ISEL-NEXT:    bgtlr 0
+; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 4
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %sub = sub nsw i64 %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
index d5e77a5cda067f..6a2c8eba5b0e87 100644
--- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -21,14 +21,16 @@ define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32slt:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB0_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB0_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB0_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -51,14 +53,16 @@ define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32ult:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB1_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB1_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB1_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB1_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB1_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -81,14 +85,14 @@ define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32sle:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB2_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB2_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB2_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB2_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB2_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -111,14 +115,14 @@ define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32ule:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB3_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB3_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB3_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB3_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB3_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -145,10 +149,9 @@ define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3,
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 6, 2
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB4_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
 ; CHECK-NO-ISEL-NEXT:  .LBB4_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -171,14 +174,14 @@ define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32sge:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB5_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB5_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB5_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB5_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB5_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -201,14 +204,14 @@ define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32uge:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB6_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB6_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB6_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB6_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB6_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -231,14 +234,16 @@ define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32sgt:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB7_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB7_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB7_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB7_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB7_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -261,14 +266,16 @@ define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3
 ; CHECK-NO-ISEL-LABEL: testi32ugt:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpw 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB8_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB8_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB8_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB8_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB8_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i32 %c3, %c4
@@ -321,14 +328,16 @@ define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64slt:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB10_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB10_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB10_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB10_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB10_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -351,14 +360,16 @@ define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64ult:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB11_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB11_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB11_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB11_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB11_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -381,14 +392,14 @@ define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64sle:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB12_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB12_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB12_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB12_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB12_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -411,14 +422,14 @@ define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64ule:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB13_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB13_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB13_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB13_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB13_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -445,10 +456,9 @@ define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 6, 2
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB14_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
 ; CHECK-NO-ISEL-NEXT:  .LBB14_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -471,14 +481,14 @@ define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64sge:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB15_2
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB15_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB15_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB15_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB15_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -501,14 +511,14 @@ define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64uge:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crorc 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB16_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB16_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB16_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB16_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:  .LBB16_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -531,14 +541,16 @@ define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0
 ; CHECK-NO-ISEL-LABEL: testi64sgt:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpd 5, 6
-; CHECK-NO-ISEL-NEXT:    cmpd 1, 3, 4
-; CHECK-NO-ISEL-NEXT:    crandc 20, 2, 6
-; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB17_2
+; CHECK-NO-ISEL-NEXT:    bc 4, 2, .LBB17_3
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT:    cmpd 3, 4
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB17_3
+; CHECK-NO-ISEL-NEXT:  # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
-; CHECK-NO-ISEL-NEXT:  .LBB17_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT:  .LBB17_3: # %entry
+; CHECK-NO-ISEL-NEXT:    mr 7, 8
+; CHECK-NO-ISEL-NEXT:    mr 3, 7
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = icmp eq i64 %c3, %c4
@@ -561,14 +573,16 @@ define i64 @testi64ugt(i64...
[truncated]

github-actions · 2024-03-15T05:41:47Z

✅ With the latest revision this PR passed the C/C++ code formatter.

chenzheng1030 · 2024-03-25T01:52:00Z

llvm/lib/Target/PowerPC/PPCExpandISEL.cpp

-static cl::opt<bool>
-    GenerateISEL("ppc-gen-isel",
-                 cl::desc("Enable generating the ISEL instruction."),
-                 cl::init(true), cl::Hidden);


As a first step, why not just set the default value to false here?

If we don't get any regressions, then as a follow up, we can remove the pass?

The option is controlling whether to generate isel instruction rather than enabling this pass. I've moved this option to PPCInstrInfo where in my view is a proper place.

chenzheng1030

LG. Assuming this does not have negative impact on the performance.
Thanks for cleaning this up.

llvmbot added the backend:PowerPC label Mar 7, 2024

bzEq marked this pull request as draft March 7, 2024 09:04

bzEq force-pushed the remove-expand-isel-pass branch from bc8622e to e7b8f70 Compare March 7, 2024 09:05

bzEq changed the title ~~[PowerPC] Instruction selector also considers ppc-gen-isel option~~ [PowerPC] Instruction selector should also consider ppc-gen-isel option Mar 7, 2024

bzEq force-pushed the remove-expand-isel-pass branch from e7b8f70 to ac376a9 Compare March 15, 2024 05:39

bzEq changed the title ~~[PowerPC] Instruction selector should also consider ppc-gen-isel option~~ [PowerPC] Retire PPCExpandISel pass Mar 15, 2024

bzEq force-pushed the remove-expand-isel-pass branch from ac376a9 to 8cd62c8 Compare March 15, 2024 05:48

bzEq requested review from ecnelises, chenzheng1030, RolandF77, stefanp-ibm, amy-kwan and lei137 March 19, 2024 02:47

bzEq marked this pull request as ready for review March 19, 2024 02:48

bzEq changed the title ~~[PowerPC] Retire PPCExpandISel pass~~ [PowerPC][RFC] Retire PPCExpandISel pass Mar 19, 2024

chenzheng1030 reviewed Mar 25, 2024

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bzEq and others added 3 commits March 26, 2024 14:44

Instruction selector also considers ppc-gen-isel option

b28e1c3

Retire PPCExpandISel

f89dfda

Use +-isel to control isel generation only

26f5727

bzEq force-pushed the remove-expand-isel-pass branch from 8cd62c8 to 26f5727 Compare March 26, 2024 07:00

bzEq requested a review from chenzheng1030 March 26, 2024 07:00

bzEq changed the title ~~[PowerPC][RFC] Retire PPCExpandISel pass~~ [PowerPC] Retire PPCExpandISel pass Apr 13, 2024

chenzheng1030 approved these changes Apr 22, 2024

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[PowerPC] Retire PPCExpandISel pass #84289

[PowerPC] Retire PPCExpandISel pass #84289

bzEq commented Mar 7, 2024 •

edited

llvmbot commented Mar 7, 2024

github-actions bot commented Mar 15, 2024 •

edited

chenzheng1030 Mar 25, 2024

bzEq Mar 25, 2024

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[PowerPC] Retire PPCExpandISel pass #84289

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[PowerPC] Retire PPCExpandISel pass #84289

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bzEq commented Mar 7, 2024 • edited

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github-actions bot commented Mar 15, 2024 • edited

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bzEq commented Mar 7, 2024 •

edited

github-actions bot commented Mar 15, 2024 •

edited