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release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes #84698

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Merged
merged 1 commit into from
Mar 13, 2024
Merged

release/18.x: [X86] combineAndShuffleNot - ensure the type is legal before create X86ISD::ANDNP target nodes #84698

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11 changes: 9 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -47878,6 +47878,7 @@ static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
SDValue X, Y;
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();

if (SDValue Not = GetNot(N0)) {
X = Not;
Expand All @@ -47891,9 +47892,11 @@ static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
X = DAG.getBitcast(VT, X);
Y = DAG.getBitcast(VT, Y);
SDLoc DL(N);

// We do not split for SSE at all, but we need to split vectors for AVX1 and
// AVX2.
if (!Subtarget.useAVX512Regs() && VT.is512BitVector()) {
if (!Subtarget.useAVX512Regs() && VT.is512BitVector() &&
TLI.isTypeLegal(VT.getHalfNumVectorElementsVT(*DAG.getContext()))) {
SDValue LoX, HiX;
std::tie(LoX, HiX) = splitVector(X, DAG, DL);
SDValue LoY, HiY;
Expand All @@ -47903,7 +47906,11 @@ static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
SDValue HiV = DAG.getNode(X86ISD::ANDNP, DL, SplitVT, {HiX, HiY});
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, {LoV, HiV});
}
return DAG.getNode(X86ISD::ANDNP, DL, VT, {X, Y});

if (TLI.isTypeLegal(VT))
return DAG.getNode(X86ISD::ANDNP, DL, VT, {X, Y});

return SDValue();
}

// Try to widen AND, OR and XOR nodes to VT in order to remove casts around
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19 changes: 19 additions & 0 deletions llvm/test/CodeGen/X86/combine-and.ll
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Expand Up @@ -1171,6 +1171,25 @@ define <4 x i32> @neg_scalar_broadcast_two_uses(i32 %a0, <4 x i32> %a1, ptr %a2)
ret <4 x i32> %4
}

; PR84660 - check for illegal types
define <2 x i128> @neg_scalar_broadcast_illegaltype(i128 %arg) {
; CHECK-LABEL: neg_scalar_broadcast_illegaltype:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notl %esi
; CHECK-NEXT: andl $1, %esi
; CHECK-NEXT: movq %rsi, 16(%rdi)
; CHECK-NEXT: movq %rsi, (%rdi)
; CHECK-NEXT: movq $0, 24(%rdi)
; CHECK-NEXT: movq $0, 8(%rdi)
; CHECK-NEXT: retq
%i = xor i128 %arg, 1
%i1 = insertelement <2 x i128> zeroinitializer, i128 %i, i64 0
%i2 = shufflevector <2 x i128> %i1, <2 x i128> zeroinitializer, <2 x i32> zeroinitializer
%i3 = and <2 x i128> <i128 1, i128 1>, %i2
ret <2 x i128> %i3
}

define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {
; SSE-LABEL: andnp_xx:
; SSE: # %bb.0:
Expand Down