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[AArch64][SME] Don't mark 'smstart za' as using/defining VG. #84775

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Merged
merged 2 commits into from
Mar 13, 2024
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[AArch64][SME] Don't mark 'smstart za' as using/defining VG. #84775

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a8ca1e3
[AArch64][SME] Don't mark 'smstart za' as using/defining VG.
sdesmalen-arm Mar 8, 2024
35b8f46
rephrase comment
sdesmalen-arm Mar 12, 2024
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12 changes: 11 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7751,14 +7751,24 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
// register allocator to pass call args in callee saved regs, without extra
// copies to avoid these fake clobbers of actually-preserved GPRs.
if (MI.getOpcode() == AArch64::MSRpstatesvcrImm1 ||
MI.getOpcode() == AArch64::MSRpstatePseudo)
MI.getOpcode() == AArch64::MSRpstatePseudo) {
for (unsigned I = MI.getNumOperands() - 1; I > 0; --I)
if (MachineOperand &MO = MI.getOperand(I);
MO.isReg() && MO.isImplicit() && MO.isDef() &&
(AArch64::GPR32RegClass.contains(MO.getReg()) ||
AArch64::GPR64RegClass.contains(MO.getReg())))
MI.removeOperand(I);

// The SVE vector length can change when entering/leaving streaming mode.
if (MI.getOperand(0).getImm() == AArch64SVCR::SVCRSM ||
MI.getOperand(0).getImm() == AArch64SVCR::SVCRSMZA) {
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
/*IsImplicit=*/true));
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/true,
/*IsImplicit=*/true));
}
}

// Add an implicit use of 'VG' for ADDXri/SUBXri, which are instructions that
// have nothing to do with VG, were it not that they are used to materialise a
// frame-address. If they contain a frame-index to a scalable vector, this
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -223,8 +223,6 @@ def MSRpstatesvcrImm1
let Inst{8} = imm;
let Inst{7-5} = 0b011; // op2
let hasPostISelHook = 1;
let Uses = [VG];
let Defs = [VG];
}

def : InstAlias<"smstart", (MSRpstatesvcrImm1 0b011, 0b1)>;
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24 changes: 24 additions & 0 deletions llvm/test/CodeGen/AArch64/sme-write-vg.ll
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@@ -0,0 +1,24 @@
; RUN: llc -mattr=+sme -stop-after=finalize-isel < %s | FileCheck %s

target triple = "aarch64"

; Check that we don't define VG for 'smstart za' and 'smstop za'
define void @smstart_za() "aarch64_new_za" nounwind {
; CHECK-LABEL: name: smstart_za
; CHECK-NOT: implicit-def {{[^,]*}}$vg
ret void
}

; Check that we do define VG for 'smstart sm' and 'smstop sm'
define void @smstart_sm() nounwind {
; CHECK-LABEL: name: smstart_sm
; CHECK: MSRpstatesvcrImm1 1, 1,
; CHECK-SAME: implicit-def {{[^,]*}}$vg
; CHECK: MSRpstatesvcrImm1 1, 0,
; CHECK-SAME: implicit-def {{[^,]*}}$vg
call void @require_sm()
ret void
}

declare void @require_sm() "aarch64_pstate_sm_enabled"
declare void @require_za() "aarch64_inout_za"