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12 changes: 10 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4007,8 +4007,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,

// For SMAX, if CstLow is non-negative we know the result will be
// non-negative and thus all sign bits are 0.
// TODO: There's an equivalent of this for smin with negative constant for
// known ones.
if (IsMax && CstLow) {
const APInt &ValueLow = CstLow->getAPIntValue();
if (ValueLow.isNonNegative()) {
Expand All @@ -4017,6 +4015,16 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
}

// For SMIN, if CstHigh is negative we know the result will be
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I don't understand why any of this SMIN/SMAX handling code is needed, except for the call to KnownBits::smin/smax. Those functions are optimal, and the code here does not seem to use any knowledge that is not captured by KnownBits info.

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@topperc topperc Mar 19, 2024

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It's possible to know the LHS has some number of sign bits without knowing whether it is positive or negative. Here's the patch that added the SMAX code https://reviews.llvm.org/D126896

The issue was that we knew the sign bit of the smax was zero before type legalization when the type was i32. This turned a sext into a sext. Then we promoted to i64 and known bits would only say bit 63 of the i64 smax was known zero. That patch made compute known bits say at least 63:31 were known zero to match what we knew before type legalization.

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Thanks - I see now that using numsignbits info does let it deduce more stuff than KnownBits can.

// negative and thus all sign bits are 1.
if (!IsMax && CstHigh) {
const APInt &ValueHigh = CstHigh->getAPIntValue();
if (ValueHigh.isNegative()) {
unsigned SignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
Known.One.setHighBits(std::min(SignBits, ValueHigh.getNumSignBits()));
}
}

break;
}
case ISD::UINT_TO_FP: {
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