Skip to content

[TableGen][SchedMachineModel] Improve way to create WriteLatencyTable. #86654

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from

Conversation

lcvon007
Copy link
Contributor

Tablegen will generate xxxWriteLatencyTable to record the
latency information for schedule class in xxxGenSubtargetInfo.inc,
and element in latency table is {Cycles, WriteResourceID}, each
target may have multiple processors using different SchedModels,
and WriteResourceId will not zero if any of SchedModel define
ReadAdvance that its ValidWrites includes SchedWrite
(as the old hasReadOfWrite function does).

Use the new method(Only use currect ProcModel) to check if we
hasReadWrite doesn't affect the usage of LatencyTable, and it
has two good points:

  1. It doesn't need traverse all the ProcModels
  2. It may generate simpler latency table with less elements.

Tablegen will generate xxxWriteLatencyTable to record the
latency information for schedule class in xxxGenSubtargetInfo.inc,
and element in latency table is {Cycles, WriteResourceID}, each
target may have multiple processors using different SchedModels,
and WriteResourceId will not zero if any of SchedModel define
ReadAdvance that its ValidWrites includes SchedWrite
(as the old hasReadOfWrite function does).

Use the new method(Only use currect ProcModel) to check if we
hasReadWrite doesn't affect the usage of LatencyTable, and it
has two good points:
1. It doesn't need traverse all the ProcModels
2. It may generate simpler latency table with less elements.
@lcvon007 lcvon007 requested review from zixuan-wu and atrick March 26, 2024 11:55
@lcvon007
Copy link
Contributor Author

I have compared the element number in each target's LatencyTable(such as RISCVWriteLatencyTable) in xxxGenSubtargetInfo.inc(such as RISCVWriteLatencyTable) before and after optimization. The result is as follow:
image

@lcvon007
Copy link
Contributor Author

lcvon007 commented Mar 26, 2024

TargetSchedModel::computeOperandLatency in TargetSchedule.cpp will use the WriteResourceID in LatencyTable, and it doesn't affect the logic when calling STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID) after change.

@lcvon007 lcvon007 requested a review from topperc March 27, 2024 01:14
@lcvon007
Copy link
Contributor Author

lcvon007 commented Apr 1, 2024

hi all, may you please help review this MR? thanks very much. @zixuan-wu @atrick @topperc

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant