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[RISCV] Model vd as a src for some Zvk* instructions in MC layer. #86710
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Some Zvk instructions use vd as a source regardless of tail policy. Model this in the MC layer. We already do this for FMA for example.
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesSome Zvk instructions use vd as a source regardless of tail policy. Model this in the MC layer. We already do this for FMA for example. Full diff: https://github.com/llvm/llvm-project/pull/86710.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 875f2e382d54fe..e68fb42ece9f02 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -531,14 +531,6 @@ class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
: RVInstV<funct6, vs1, opv, (outs VR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2$vm">;
-
-// op vd, vs2 (use vs1 as instruction encoding)
-class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
- : RVInstV<funct6, vs1, opv, (outs VR:$vd),
- (ins VR:$vs2), opcodestr,
- "$vd, $vs2"> {
- let vm = 1;
-}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 035ce63e91e91e..ee9c7338d5fd9d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -67,6 +67,16 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
let Inst{6-0} = OPC_OP_P.Value;
}
+// op vd, vs2, vs1
+class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd_wb),
+ (ins VR:$vd, VR:$vs2, VR:$vs1),
+ opcodestr, "$vd, $vs2, $vs1"> {
+ let Constraints = "$vd = $vd_wb";
+ let vm = 1;
+ let Inst{6-0} = OPC_OP_P.Value;
+}
+
// op vd, vs2, imm
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
: VALUVINoVm<funct6, opcodestr, optype> {
@@ -74,16 +84,32 @@ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
let Inst{14-12} = OPMVV.Value;
}
-// op vd, vs2 (use vs1 as instruction encoding)
-class PALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
- : VALUVs2NoVm<funct6, vs1, opv, opcodestr> {
+// op vd, vs2, imm where vd is also a source regardless of tail policy
+class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
+ : RVInstIVI<funct6, (outs VR:$vd_wb),
+ (ins VR:$vd, VR:$vs2, optype:$imm),
+ opcodestr, "$vd, $vs2, $imm"> {
+ let Constraints = "$vd = $vd_wb";
+ let vm = 1;
+ let Inst{6-0} = OPC_OP_P.Value;
+ let Inst{14-12} = OPMVV.Value;
+}
+
+// op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
+// regardless of tail policy
+class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
+ string opcodestr>
+ : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
+ opcodestr, "$vd, $vs2"> {
+ let Constraints = "$vd = $vd_wb";
+ let vm = 1;
let Inst{6-0} = OPC_OP_P.Value;
}
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
- def NAME # _VV : PALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
- def NAME # _VS : PALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
+ def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">;
+ def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -114,14 +140,14 @@ let Predicates = [HasStdExtZvkb] in {
} // Predicates = [HasStdExtZvkb]
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
- def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">;
- def VGMUL_VV : PALUVs2NoVm<0b101000, 0b10001, OPMVV, "vgmul.vv">;
+ def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">;
+ def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">;
} // Predicates = [HasStdExtZvkg]
let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = NoConstraint in {
- def VSHA2CH_VV : PALUVVNoVm<0b101110, OPMVV, "vsha2ch.vv">;
- def VSHA2CL_VV : PALUVVNoVm<0b101111, OPMVV, "vsha2cl.vv">;
- def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">;
+ def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">;
+ def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">;
+ def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]
let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
@@ -130,8 +156,8 @@ let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>;
- def VAESKF2_VI : PALUVINoVm<0b101010, "vaeskf2.vi", uimm5>;
- def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
+ def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>;
+ def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">;
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
@@ -140,7 +166,7 @@ let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in {
- def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
+ def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
} // Predicates = [HasStdExtZvksh]
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LGTM, thanks!
Are you planning on doing this on the Pseudo MI level too? |
I already did 8551454 there it was just a rename since the tied constraint was already needed for correctness. |
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I missed that. LGTM
Some Zvk instructions use vd as a source regardless of tail policy. Model this in the MC layer. We already do this for FMA for example.